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在我的设计实现期间出现此警告(位于底部),该设计使用从Mini-ITX平台板定义文件中获取的默认IO分配。
正如其他帖子所提到的那样,这是一个完全无足轻重的警告,不值得关注。 MIO的任务在我的设计中如下: [1-6] =四路SPI,LVCMOS18 [16-27] = Enet0,HSTL I 18 [28-39] = USB 0,LVCMOS18 [40-45] = SD0,LVCMOS18 [48-49] = UART1,LVCMOS18 [50-51] = I2C0,LVCMOS18 我按照下面的建议并禁用了对PLIO *的DRC检查,这让我感到有点不安......但至少现在我可以生成一个位文件并将我的设计导出到SDK。 底线问题:这个问题似乎至少从2015年开始......可能更早。 我认为它仍然在2016.2和2016.4中发生 - 什么时候会被修复,所以我们不必继续禁用DRC检查? 推荐修复: https://www.xilinx.com/support/answers/63367.html set_property IS_ENABLED 0 [get_drc_checks PLIO *] 我的设计警告: [放置30-12]找到具有多个IO标准的IO总线FIXED_IO_MIO。 与此总线相关联的部件有:IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的FIXED_IO_MIO [53] LVCMOS18 FIXED_IO_MIO [52] LVCMOS18 FIXED_IO_MIO [51] LVCMOS18 FIXED_IO_MIO [50] LVCMOS18 FIXED_IO_MIO [49] LVCMOS18 FIXED_IO_MIO [48] LVCMOS18 FIXED_IO_MIO IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的[47] IOSTANDARD的LVCMOS18 FIXED_IO_MIO [46] IOSTANDARD的LVCMOS18 FIXED_IO_MIO [45] LVCMOS18 FIXED_IO_MIO [44] LVCMOS18 FIXED_IO_MIO [43] LVCMOS18 FIXED_IO_MIO [42] LVCMOS18 FIXED_IO_MIO [41] LVCMOS18 FIXED_IO_MIO [ IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的] IOSTANDARD 40 LVCMOS18 FIXED_IO_MIO [39 IOSTANDARD的] LVCMOS18 FIXED_IO_MIO [38] LVCMOS18 FIXED_IO_MIO [37] LVCMOS18 FIXED_IO_MIO [36] LVCMOS18 FIXED_IO_MIO [35] LVCMOS18 FIXED_IO_MIO [34] LVCMOS18 FIXED_IO_MIO [33 IOS标准LVCMOS18 FIXED_IO_MIO [32] IOStandard LVCMOS18 FIXED_IO_MIO [31] IOStandard LVCMOS18 FIXED_IO_MIO [30] IOStandard LVCMOS18的IOStandard LVCMOS18 FIXED_IO_MIO [32] IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的FIXED_IO_MIO [29] IOSTANDARD的LVCMOS18 FIXED_IO_MIO [28] LVCMOS18 FIXED_IO_MIO [27] HSTL_I_18 FIXED_IO_MIO [26] HSTL_I_18 FIXED_IO_MIO [25] HSTL_I_18 FIXED_IO_MIO [24] HSTL_I_18 FIXED_IO_MIO IOSTANDARD HSTL_I_18 FIXED_IO_MIO的[23] IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的[22] IOSTANDARD的HSTL_I_18 FIXED_IO_MIO [21] IOSTANDARD的HSTL_I_18 FIXED_IO_MIO [20] HSTL_I_18 FIXED_IO_MIO [19] HSTL_I_18 FIXED_IO_MIO [18] HSTL_I_18 FIXED_IO_MIO [17] HSTL_I_18 FIXED_IO_MIO [16] HSTL_I_18 FIXED_IO_MIO [ IOSTANDARD的IOSTANDARD的IOSTANDARD的IOSTANDARD的] IOSTANDARD 15 LVCMOS18 FIXED_IO_MIO [14 IOSTANDARD的] LVCMOS18 FIXED_IO_MIO [13] LVCMOS18 FIXED_IO_MIO [12] LVCMOS18 FIXED_IO_MIO [11] LVCMOS18 FIXED_IO_MIO [10] LVCMOS18 FIXED_IO_MIO [9] IOSTANDARD LVCMOS18 FIXED_IO_MIO [8 IOS标准LVCMOS18的FIXED_IO_MIO [7] IOStandard LVCMOS18 FIXED_IO_MIO [6] IOStandard LVCMOS18 FIXED_IO_MIO [5] IOStandard L的IOStandard LVCMOS18 FIXED_IO_MIO [7] 国际标准LVCMOS18的IOS标准LVCMOS18 FIXED_IO_MIO [2]的IOS标准LVCMOS18 FIXED_IO_MIO [2]的IOS标准LVCMOS18 FIXED_IO_MIO [1]的IOS标准LVCMOS18的FIXED_IO_MIO [4]和IOStandard LVCMOS18的FIXED_IO_MIO [0]的VCMOS18 FIXED_IO_MIO [4] 以上来自于谷歌翻译 以下为原文 This warning (below at bottom) comes up during implementation for my design which uses the default IO assignments taken from the Mini-ITX platform board definition files. As other postings here have mentioned, it is a completely trivial warning and no cause for concern. The MIO assignments are as follows in my design: [1-6] = Quad SPI, LVCMOS18 [16-27] = Enet0, HSTL I 18 [28-39] = USB 0, LVCMOS18 [40-45] = SD0, LVCMOS18 [48-49] = UART1, LVCMOS18 [50-51] = I2C0, LVCMOS18 I followed the advice below and disabled DRC checks for PLIO*, which leaves me feeling somewhat uneasy... but at least now I can produce a bitfile and export my design to SDK. Bottom line question: This issue appears to have been around since at least 2015.3... perhaps earlier. And I see it still occurring in both 2016.2 and 2016.4 - When will it be fixed so we don't have to keep disabling DRC checks? Recommended fix: https://www.xilinx.com/support/answers/63367.html set_property IS_ENABLED 0 [get_drc_checks PLIO*] Warning from my design: [Place 30-12] An IO Bus FIXED_IO_MIO with more than one IO standard is found. Components associated with this bus are: FIXED_IO_MIO[53] of IOStandard LVCMOS18 FIXED_IO_MIO[52] of IOStandard LVCMOS18 FIXED_IO_MIO[51] of IOStandard LVCMOS18 FIXED_IO_MIO[50] of IOStandard LVCMOS18 FIXED_IO_MIO[49] of IOStandard LVCMOS18 FIXED_IO_MIO[48] of IOStandard LVCMOS18 FIXED_IO_MIO[47] of IOStandard LVCMOS18 FIXED_IO_MIO[46] of IOStandard LVCMOS18 FIXED_IO_MIO[45] of IOStandard LVCMOS18 FIXED_IO_MIO[44] of IOStandard LVCMOS18 FIXED_IO_MIO[43] of IOStandard LVCMOS18 FIXED_IO_MIO[42] of IOStandard LVCMOS18 FIXED_IO_MIO[41] of IOStandard LVCMOS18 FIXED_IO_MIO[40] of IOStandard LVCMOS18 FIXED_IO_MIO[39] of IOStandard LVCMOS18 FIXED_IO_MIO[38] of IOStandard LVCMOS18 FIXED_IO_MIO[37] of IOStandard LVCMOS18 FIXED_IO_MIO[36] of IOStandard LVCMOS18 FIXED_IO_MIO[35] of IOStandard LVCMOS18 FIXED_IO_MIO[34] of IOStandard LVCMOS18 FIXED_IO_MIO[33] of IOStandard LVCMOS18 FIXED_IO_MIO[32] of IOStandard LVCMOS18 FIXED_IO_MIO[31] of IOStandard LVCMOS18 FIXED_IO_MIO[30] of IOStandard LVCMOS18 FIXED_IO_MIO[29] of IOStandard LVCMOS18 FIXED_IO_MIO[28] of IOStandard LVCMOS18 FIXED_IO_MIO[27] of IOStandard HSTL_I_18 FIXED_IO_MIO[26] of IOStandard HSTL_I_18 FIXED_IO_MIO[25] of IOStandard HSTL_I_18 FIXED_IO_MIO[24] of IOStandard HSTL_I_18 FIXED_IO_MIO[23] of IOStandard HSTL_I_18 FIXED_IO_MIO[22] of IOStandard HSTL_I_18 FIXED_IO_MIO[21] of IOStandard HSTL_I_18 FIXED_IO_MIO[20] of IOStandard HSTL_I_18 FIXED_IO_MIO[19] of IOStandard HSTL_I_18 FIXED_IO_MIO[18] of IOStandard HSTL_I_18 FIXED_IO_MIO[17] of IOStandard HSTL_I_18 FIXED_IO_MIO[16] of IOStandard HSTL_I_18 FIXED_IO_MIO[15] of IOStandard LVCMOS18 FIXED_IO_MIO[14] of IOStandard LVCMOS18 FIXED_IO_MIO[13] of IOStandard LVCMOS18 FIXED_IO_MIO[12] of IOStandard LVCMOS18 FIXED_IO_MIO[11] of IOStandard LVCMOS18 FIXED_IO_MIO[10] of IOStandard LVCMOS18 FIXED_IO_MIO[9] of IOStandard LVCMOS18 FIXED_IO_MIO[8] of IOStandard LVCMOS18 FIXED_IO_MIO[7] of IOStandard LVCMOS18 FIXED_IO_MIO[6] of IOStandard LVCMOS18 FIXED_IO_MIO[5] of IOStandard LVCMOS18 FIXED_IO_MIO[4] of IOStandard LVCMOS18 FIXED_IO_MIO[3] of IOStandard LVCMOS18 FIXED_IO_MIO[2] of IOStandard LVCMOS18 FIXED_IO_MIO[1] of IOStandard LVCMOS18 and FIXED_IO_MIO[0] of IOStandard LVCMOS18 |
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3个回答
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嗨@ rmm92vt,
此警告仍将在Vivado的未来版本中。 原因是DRC是正确的。 有问题的公共汽车有各种IOS标准。 这被标记为DRC中的警告。 但是在AR#63367的情况下,放置位于两个不同的库中,因此它是有效的,因此没有错误。 这就是为什么你可以在这种特殊情况下删除此警告的原因。 问候, 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复,kudo,并接受作为解决方案。 以上来自于谷歌翻译 以下为原文 Hi @rmm92vt, This warning will still be in future version of Vivado. The reason for that is that the DRC is correct. The bus in question has a mix of IOStandards. This is flagged as a warning in DRCs. But in the case of the AR#63367, the placement is in two different banks so it is valid, hence no errors. That is the reason why you can remove this warning in this particular case. Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. |
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是的,刚果民主共和国可能在法律上是正确的......但是,在我的设计中,它是否对它现有的信息有点无知?
它应该能够像我们一样确定银行业规则没有被打破。 因此没有害处,我应该被允许创建一个位文件。 就像现在一样,如果不发出这个TCL命令,我就无法得到一个位文件。 每次重新启动工具(或迁移到脚本驱动的构建流程)时,我都需要重新发出它。 即使这不属于DRC,那么它不应该落在我用来创建MIO配置的ZYNQ7自定义向导上吗? 它创造了一种情况,它应该知道会阻止我制作一个位文件。 以上来自于谷歌翻译 以下为原文 Yes, DRC may be legally correct... but isn't it being a bit ignorant of information readily available to it in my design? It should be able to determine just as we have that the banking rules have not been broken. And therefore no harm and I should be allowed to create a bitfile. As it is now, I can't get a bitfile without issuing this TCL command. And I need to reissue it each time I restart the tool (or migrate to a script-driven build flow). And even if this doesn't fall on DRC, then shouldn't it fall on the ZYNQ7 Customization Wizard I used to create the MIO configuration in the first place? It's creating a situation that it should KNOW will prevent me from making a bitfile. |
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HI @ rmm92vt,
如果您无法生成比特流,那应该是因为您在同一个银行中有不同的标准。 但是,这可能是一种改进,可以防止GUI生成无效的配置。 我会检查要求增强。 问候, 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复,kudo,并接受作为解决方案。 以上来自于谷歌翻译 以下为原文 HI @rmm92vt, If you cannot generate the bitstream, it should be because you have different standard in the same bank. But yes, this could be an improvement to prevent the GUI from generating a non-valid configuration. I will check to ask for enhancement. Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. |
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