在vivado.log中找不到错误

你好@ pumaju1808
由于之前的警告和严重警告，错误存在。
请参阅AR的以下链接以解决这些警告和严重警告。
https://www.xilinx.com/support/answers/56169.html
https://www.xilinx.com/support/answers/53445.html
希望这可以帮助
问候
罗希特
RegardsRohit -------------------------------------------------
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答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K--
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以下为原文

Hi @pumaju1808
 
The error is there due to previous warnings and critical warnings . Refer to the below link of the ARs to resolve those warnings and critical warnings.
https://www.xilinx.com/support/answers/56169.html
https://www.xilinx.com/support/answers/53445.html
 
Hope this helps
 
Regards
Rohit
 
Regards
Rohit
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感谢thakurr，为什么在其他情况下，也有警告和严重警告，但即使这样，它也会生成位文件？这里有什么规则，当警告或严重警告成为错误并停止P＆amp; R过程时
？谢谢



以下为原文

thanks thakurr,

Why in other cases , also there are warning and critical warnings as well , but even so , it generates the bit file?, what is the rule here, when warning or critical warning becomes an error and stop the P&R process ?

Thanks

你好@ pumaju1808
有时它还取决于警告的严重程度和严重警告。
如果设计正在通过比特流，那么关键警告就是不确定它是否可以在电路板上正常工作。
问候
罗希特
RegardsRohit -------------------------------------------------
---------------------------------------------请注意 - 请注明
答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K--
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以下为原文

Hi @pumaju1808
 
Some times it depends on the severity of the warnings and critical warnings also. With the critical warnings if design is passing bit stream, it is not sure it will work fine on the board.
 
Regards
Rohit
Regards
Rohit
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@ pumaju1808
请参阅AR＃65179和AR＃53981并查看是否有帮助.https：//www.xilinx.com/support/answers/65179.html
https://www.xilinx.com/support/answers/53981.htmlThanks，
ASIT
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以下为原文

@pumaju1808
Please refer to AR#65179 and AR#53981 and see if it helps.
https://www.xilinx.com/support/answers/65179.html
https://www.xilinx.com/support/answers/53981.html

Thanks,
Asit
 
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你好@ pumaju1808
从日志中我看到IO时钟布局器发生故障。
尝试在合成设计上运行以下命令，看看它是否因更好的消息传递而失败
opt_design
place_ports
如果你可以上传位于.runs  - > impl_1文件夹中的_opt.dcp，我可以检查一下。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi @pumaju1808
 
From the log I see that the IO clock placer is failing.
 
Try running below commands on synthesized design and see if it fails with better messaging
 
opt_design
place_ports
 
If you can upload _opt.dcp located in .runs --> impl_1 folder, I can check the same.
Thanks,
Deepika.
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嗨Deepika
我的dcp是330 MB大小，我无法上传，因为我超大了允许的最大值，你知道怎么做吗？
谢谢，
JC



以下为原文

Hi Deepika
 
My dcp is 330 MB size, I can't uploaded since I oversized the maximum allowed, do you know how?
 
Thanks,
JC

@ pumaju1808，
分享您的电子邮件ID，以便我们向您发送您的EZmove链接凭据，您可以从中发送您的dcp文件（330 MB）。谢谢，
ASIT
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以下为原文

@pumaju1808,
 
Share your email ID so that we can send you your credentials of EZmove link, from which you will be able to send your dcp file(330 MB).

Thanks,
Asit
 
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嗨，
我给你发了一条私信，
谢谢，



以下为原文

Hi,
 
I sent you a private message,
 
Thanks,

@ pumaju1808
谢谢，我收到了你的消息。
我已向您发送了一封电子邮件，其中包含EZmove的登录凭据。
问候，
ASIT
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以下为原文

@pumaju1808
 
Thanks, I received your message. I have sent you an email with login credentials of EZmove.
 
Regards,
Asit
 
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