全局时钟脊柱由2个时钟缓冲器共享

嗨，
我能够获得设计传递place_design，BUFG在设计中的位置如下所示
BUFG实例 “u_fpga_display / u_DP_sor0 / u_gtx_clk /安装/ clkout1_buf” 被置于 “BUFGCTRL_X0Y23” BUFG实例 “u_fpga_dut_clk / RG0_clk_bufg” 被置于 “BUFGCTRL_X0Y81” BUFG实例 “u_fpga_dut_clk / RG2_clk_bufg” 被置于 “BUFGCTRL_X0Y33” BUFG实例“u_fpga_dut_clk /
RG3_clk_bufg “被置于 ”u_fpga_dut_clk / bufgmux_sf0_clk_1 “被置于 ”BUFGCTRL_X0Y30“ BUFG实例” u_fpga_dut_clk / bufgmux_sf0_clk_0 “被置于 ”BUFGCTRL_X0Y31 u_fpga_dut_clk / bufg_xtal “被置于 ”BUFGCTRL_X0Y34 BUFGCTRL_X0Y19“ BUFG实例”“ BUFG实例”“ BUFG实例”
u_fpga_dut_clk / bufgmux_sf1_clk_0" 被置于 “BUFGCTRL_X0Y29” BUFG实例 “u_fpga_dut_clk / bufgmux_sf1_clk_1” 被置于 “BUFGCTRL_X0Y28” BUFG实例 “u_fpga_dut_clk / bufgmux_sf2_clk_0” 被置于 “BUFGCTRL_X0Y27” BUFG实例 “u_fpga_dut_clk / bufgmux_sf2_clk_1” 被置于 “BUFGCTRL_X0Y26” BUFG
实例“u_fpga_dut_clk / bufgmux_sf3_clk_0”位于“BUFGCTRL_X0Y25”bufg实例“u_fpga_dut_clk / bufgmux_sf3_clk_1”位于“BUFGC”
TRL_X0Y24" BUFG实例 “u_fpga_dut_clk / rg0_bufg” 被置于 “BUFGCTRL_X0Y112” BUFG实例 “u_fpga_dut_clk / rg2_bufg” 被置于 “BUFGCTRL_X0Y108” BUFG实例 “u_fpga_dut_clk / rg3_bufg” 被置于 “BUFGCTRL_X0Y109” BUFG实例 “u_fpga_dut_clk / sor0_sel” 被放置
在 “u_fpga_dut_clk / u_bufg_iodelay” 被置于 “BUFGCTRL_X0Y103” BUFG实例“u_fpga_dut_clk / u_v7_disp_hub_clk / “u_fpga_dut_clk / sor3_sel” 被置于 “BUFGCTRL_X0Y20” “u_fpga_dut_clk / sor2_sel” 被置于 “BUFGCTRL_X0Y18” “BUFGCTRL_X0Y22” BUFG实例BUFG实例BUFG实例
clkout1_buf”被置于 “u_fpga_dut_clk / u_v7_disp_hub_clk / clkout2_buf ”被置于 “BUFGCTRL_X0Y73 BUFGCTRL_X0Y72” BUFG实例“” BUFG实例 “u_fpga_dut_clk / u_v7_disp_hub_clk / clkout3_buf” 被置于 “u_fpga_dut_clk / u_v7_disp_hub_clk / clkout4_buf ”被放置在BUFGCTRL_X0Y74“ BUFG实例”
“BUFGCTRL_X0Y75”bufg实例“u_fpga_dut_clk / u_v7_dut_gclk0 / clkout2_buf”位于“BUFGCTRL_X0Y35”bufg实例“u_fpga_dut_clk / u_v7_dut_gclk0 / clkou
t3_buf”被置于 “u_fpga_dut_clk / u_v7_dut_gclk0 / clkout4_buf ”被置于 “BUFGCTRL_X0Y37 B​​UFGCTRL_X0Y36” BUFG实例“” BUFG实例 “u_fpga_dut_clk / u_v7_dut_gclk0 / clkout7_buf” 被置于 “u_fpga_dut_clk / v7_mmcm_dyn_sor_rg_hdmi_u2 / clkout3_buf ”被放置在BUFGCTRL_X0Y38“ BUFG实例”
“BUFGCTRL_X0Y32”bufg实例“u_fpga_dut_clk / v7_pll_dyn_rg_u3 / bufg”位于“BUFGCTRL_X0Y21”
如果您仍然遇到前面提到的约束的错误，那么尝试锁定上述位置的所有bufg。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi,
 
I was able to get the design pass place_design and the locations of BUFG's in the design is as below
 
bufg instance "u_fpga_display/u_DP_sor0/u_gtx_clk/inst/clkout1_buf" is placed at "BUFGCTRL_X0Y23"
bufg instance "u_fpga_dut_clk/RG0_clk_bufg" is placed at "BUFGCTRL_X0Y81"
bufg instance "u_fpga_dut_clk/RG2_clk_bufg" is placed at "BUFGCTRL_X0Y33"
bufg instance "u_fpga_dut_clk/RG3_clk_bufg" is placed at "BUFGCTRL_X0Y19"
bufg instance "u_fpga_dut_clk/bufg_xtal" is placed at "BUFGCTRL_X0Y34"
bufg instance "u_fpga_dut_clk/bufgmux_sf0_clk_0" is placed at "BUFGCTRL_X0Y31"
bufg instance "u_fpga_dut_clk/bufgmux_sf0_clk_1" is placed at "BUFGCTRL_X0Y30"
bufg instance "u_fpga_dut_clk/bufgmux_sf1_clk_0" is placed at "BUFGCTRL_X0Y29"
bufg instance "u_fpga_dut_clk/bufgmux_sf1_clk_1" is placed at "BUFGCTRL_X0Y28"
bufg instance "u_fpga_dut_clk/bufgmux_sf2_clk_0" is placed at "BUFGCTRL_X0Y27"
bufg instance "u_fpga_dut_clk/bufgmux_sf2_clk_1" is placed at "BUFGCTRL_X0Y26"
bufg instance "u_fpga_dut_clk/bufgmux_sf3_clk_0" is placed at "BUFGCTRL_X0Y25"
bufg instance "u_fpga_dut_clk/bufgmux_sf3_clk_1" is placed at "BUFGCTRL_X0Y24"
bufg instance "u_fpga_dut_clk/rg0_bufg" is placed at "BUFGCTRL_X0Y112"
bufg instance "u_fpga_dut_clk/rg2_bufg" is placed at "BUFGCTRL_X0Y108"
bufg instance "u_fpga_dut_clk/rg3_bufg" is placed at "BUFGCTRL_X0Y109"
bufg instance "u_fpga_dut_clk/sor0_sel" is placed at "BUFGCTRL_X0Y22"
bufg instance "u_fpga_dut_clk/sor2_sel" is placed at "BUFGCTRL_X0Y18"
bufg instance "u_fpga_dut_clk/sor3_sel" is placed at "BUFGCTRL_X0Y20"
bufg instance "u_fpga_dut_clk/u_bufg_iodelay" is placed at "BUFGCTRL_X0Y103"
bufg instance "u_fpga_dut_clk/u_v7_disp_hub_clk/clkout1_buf" is placed at "BUFGCTRL_X0Y72"
bufg instance "u_fpga_dut_clk/u_v7_disp_hub_clk/clkout2_buf" is placed at "BUFGCTRL_X0Y73"
bufg instance "u_fpga_dut_clk/u_v7_disp_hub_clk/clkout3_buf" is placed at "BUFGCTRL_X0Y74"
bufg instance "u_fpga_dut_clk/u_v7_disp_hub_clk/clkout4_buf" is placed at "BUFGCTRL_X0Y75"
bufg instance "u_fpga_dut_clk/u_v7_dut_gclk0/clkout2_buf" is placed at "BUFGCTRL_X0Y35"
bufg instance "u_fpga_dut_clk/u_v7_dut_gclk0/clkout3_buf" is placed at "BUFGCTRL_X0Y36"
bufg instance "u_fpga_dut_clk/u_v7_dut_gclk0/clkout4_buf" is placed at "BUFGCTRL_X0Y37"
bufg instance "u_fpga_dut_clk/u_v7_dut_gclk0/clkout7_buf" is placed at "BUFGCTRL_X0Y38"
bufg instance "u_fpga_dut_clk/v7_mmcm_dyn_sor_rg_hdmi_u2/clkout3_buf" is placed at "BUFGCTRL_X0Y32"
bufg instance "u_fpga_dut_clk/v7_pll_dyn_rg_u3/bufg" is placed at "BUFGCTRL_X0Y21"
 
If you still get errors with earlier mentioned constraints, then try locking all the bufg's at the above mentioned locations.
 
Thanks,
Deepika.
 
 
Thanks,
Deepika.
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有没有人知道这件事？



以下为原文

Is there anyone know about this?

嗨，请查看http://forums.xilinx.com/t5/Implementation/ERROR-Place-30-660-Global-clock-spines-are-oversubscribed//-p/387801
谢谢，维杰-----------------------------------------------
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以下为原文

Hi,
Please check http://forums.xilinx.com/t5/Implementation/ERROR-Place-30-660-Global-clock-spines-are-oversubscribed/td-p/387801Thanks,Vijay
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感谢您的回复。
但是现在我不能为BUFG设置约束，因为它会导致其他故障。
反正有没有绕过这个警告和错误？错误的时间对我来说也没关系。我们只想成功地制作P＆amp; R.



以下为原文

Thanks for your reply.
But now I cannot set constraint to the BUFG beacause it will cause other failures.
Is there anyway to bypass this warning and error?Bad timing is also ok for me.We just want to make the P&R successfully.

嗨，
以下是UG949。
这里重要的是用粗体字母突出显示的那个。
当需要超过16个（但少于32个）BUFG时，必须对引脚选择和放置进行一些考虑，以避免基于全局时钟线争用和/或时钟负载的放置而有任何争用资源的可能性。
与所有其他Xilinx 7系列FPGA器件一样，具有时钟功能的I / O（CCIO）及其相关的时钟管理平铺（CMT）对它们可在给定SLR内驱动的BUFG有限制。
SLR的上半部分或下半部分中的CCIO仅可以在SLR的上半部分或下半部分（分别）驱动BUFG。
因此，引脚和相关的CMT选择应该以所有SLR的上半部分或下半部分共同需要不超过16个BUFG的方式进行。
在这样做时，工具可以自动分配所有BUFG，以允许所有时钟被驱动到所有SLR而不会发生争用。
您可以打开后期综合检查点并在TCL控制台中运行opt_design，然后运行place_ports命令。
在此之后，您将能够在设备中查看BUFG，CMT等的位置。
在这里你需要确保如果你在所有SLR的上半部分中添加BUFG的数量，它应该小于16.类似地，在所有SLR的下半部分中，你可以共同拥有最多16个BUFG。
如果您可以调整/修改您的设计以满足此规则，则实施将成功完成。
如果您可以共享后期综合检查点，我可以分析设计并为您提供更多建议。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi,
 
Below is from UG949. The important thing here is the one highlighted in bold letters.
 
When more than sixteen (but fewer than thirty-two) BUFGs are required, some consideration to pin selection and placement must be done in order to avoid any chance of contention of resources based on global clocking line contention
and/or placement of clock loads.

As in all other Xilinx 7 series FPGA devices, Clock-Capable I/Os (CCIOs) and their associated Clock Management Tile (CMT) have restrictions on the BUFGs they can drive within the given SLR. CCIOs in the top or bottom half of the SLR can drive BUFGs only in the top or bottom half of the SLR (respectively). For this reason, pin and associated CMT selection
should be done in a way in which no more than sixteen BUFGs are required in either the top or bottom half of all SLRs collectively. In doing so, the tools can automatically assign all BUFGs in a way to allow all clocks to be driven to all SLRs without contention.
 
You can open post synthesis checkpoint and run opt_design followed by place_ports commands in TCL console.
 
After this you will be able to view the placement of BUFG, CMT etc in the device. Here you need to make sure that if you add the number of BUFG's in top halves of all SLR's it should be less than 16. Similarly in bottom halves of all SLR's you can have at max 16 BUFG's collectively. If you can adjust/modify your design to satisfy this rule the Implementation completes succesfully.
 
If you can share the post synthesis checkpoint, I can analyze the design and provide you more suggestions.
 
Thanks,
Deepika.
Thanks,
Deepika.
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嗨，
很抱歉因旅行而延迟回复。
我在哪里可以看到BUFG和其他细胞的位置？因为我无法在舞台上跑步。



以下为原文

Hi,
Sorry for the delay reply due to a travel.
Where can I see the place of BUFG and other cells ?Because I fail to run place stage.

嗨，
您可以打开后期综合检查点/综合设计，并在TCL控制台中运行opt_design，然后执行place_ports命令。
这将显示设备视图中的部分放置设计（IO和时钟放置）。
在此之后，您将能够在设备中查看BUFG，CMT等的位置。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi,
 
You can open post synthesis checkpoint/synthesized design and run opt_design followed by place_ports commands in TCL console. This will show you the partially placed design (IO and clock placement) in the device view.
 
After this you will be able to view the placement of BUFG, CMT etc in the device.
 
Thanks,
Deepika.
Thanks,
Deepika.
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嗨，如何与你分享dcp？



以下为原文

Hi,How to share the dcp with you?

嗨，
您可以将以下约束添加到XDC并重新运行实现
set_property LOC BUFGCTRL_X0Y108 [get_cells u_fpga_dut_clk / rg2_bufg]
set_property LOC BUFGCTRL_X0Y109 [get_cells u_fpga_dut_clk / rg3_bufg]
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi,
 
Can you add the below constraints to XDC and rerun implementation
 
set_property LOC BUFGCTRL_X0Y108 [get_cells u_fpga_dut_clk/rg2_bufg]
set_property LOC BUFGCTRL_X0Y109 [get_cells u_fpga_dut_clk/rg3_bufg]
 
Thanks,
Deepika.
Thanks,
Deepika.
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谢谢。我会试一试。



以下为原文

Thanks.I will have a try.