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大家好，
对于BUFG-BUFG级联对错误，我有[Place 30-120]次优放置。 我知道错误的发生是因为BUFG无法级联... 请参阅下面的“有问题”逻辑。 如您所见，时钟多路复用器的输出连接到时钟门控单元。 我想这就是问题所在。 那么，如何解决？ 时钟多路复用器的输出驱动几个inst0和inst1而没有任何时钟门控，但是应该为inst2选通相同的时钟（见下图）。 如何在没有放置错误的情况下实现此逻辑 谢谢！ 以上来自于谷歌翻译 以下为原文 Hi All, I've got the [Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair error. I understand that the error occurs because BUFG cannot be cascaded... Please see below the "problematic" logic. As you could see, clock mux's output is connected to the clock gated cell. I guess this is the problem. So, how to solve? The clock mux's output drives several inst0 and inst1 without any clock gating, but the same clock should be gated for inst2 (see the picture below). How to implement this logic without placement errors? Thank you! 
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13个回答
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HI @ dmitry1417
打开合成设计，在网表选项卡中，选择BUGMUX primitve并将其拖动到设备视图中，将其放置在设备中心的BUFG位置。对BUFGCE实例执行相同操作并将其放置在BUFGMUX附近的BUFG位置 location.when保存时，各个LOC约束将写入xdc文件。 ThanksBharath ------------------------------------------------- - --------------------------------------------请标记答案 如果提供的信息可以解决您的疑问/问题，请“接受为解决方案”。给予您认为有用的帖子。感谢.------------------------ -------------------------- ----------- ------------ -------------------- 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 HI @dmitry1417 Open synthesized design, In the netlist tab, select the BUGMUX primitve and drag it on the device view , place it some BUFG location at the center of the device. Do the same for the BUFGCE instance and place it on BUFG location adjacent to the BUFGMUX location. when you save , respective LOC constraints will be written into the xdc file. Thanks Bharath ---------------------------------------------------------------------------------------------- Please mark the Answer as "Accept as solution" if information provided addresses your query/concern. Give Kudos to a post which you think is helpful. ---------------------------------------------------------------------------------------------View solution in original post |
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你好@ dmitry1417
我假设您使用的是7系列设备。 如果只有2个BUFG级联，该工具应该能够为它们找到最佳位置。 BUFMUX的驱动因素有哪些？ 谢谢，迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星） 以上来自于谷歌翻译 以下为原文 Hi @dmitry1417 I assume that you are using 7 series device. If only 2 BUFG's are cascaded, the tool should be able to find optimal locations for them. What are the drivers of BUFMUX? Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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是的，这是zynq 7020
clk0和clk1是输入引脚，clk_g也进入器件的输出引脚 以上来自于谷歌翻译 以下为原文 yes, this is zynq 7020 clk0 and clk1 are input pins, clk_g also goes to output pin of the device |
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@ dmitry1417，
使用级联BUFG时需要遵循特定的规则。 请查看以下7系列时钟资源用户指南中的第35页： http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf 确保您没有违反任何规则。 你能检查一下clk驱动的其他负载吗？ --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @dmitry1417, There are specific rules which needs to be followed when using cascaded BUFG. Please check page number 35 in below 7 series clocking resource user guide: http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf Make sure you are not violating any rule. Can you check what other loads are driven by clk? --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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HI @ dmitry1417
您的设计中有多少个BUFG。您可以尝试将BUFGMUX和BUFGCE设置到相邻位置。将这些BUFG放到设备的同一半，其中clk0和clk1输入端口的IO组存在 ThanksBharath ------------------------------------------------- - --------------------------------------------请标记答案 如果提供的信息可以解决您的疑问/问题，请“接受为解决方案”。给予您认为有用的帖子。感谢.------------------------ -------------------------- ----------- ------------ -------------------- 以上来自于谷歌翻译 以下为原文 HI @dmitry1417 How many BUFG are there in your design. Can you try LOC the BUFGMUX and BUFGCE to adjacent locations.. LOC those BUFGs to the same half of the device in which the IO bank of the clk0 and clk1 input ports is present Thanks Bharath ---------------------------------------------------------------------------------------------- Please mark the Answer as "Accept as solution" if information provided addresses your query/concern. Give Kudos to a post which you think is helpful. --------------------------------------------------------------------------------------------- |
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你好@ dmitry1417
您可以使用以下约束 set_property LOC BUFGCTRL_XxYy [get_cells bufg_instance_name] 谢谢，迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星） 以上来自于谷歌翻译 以下为原文 Hi @dmitry1417 You can use below constraint set_property LOC BUFGCTRL_XxYy [get_cells bufg_instance_name] Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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至于BUFGCTRL_XxYy，是XxYy的位置坐标吗？
怎么知道XxYy？ 我怎么能通过GUI做同样的事情？ 谢谢 以上来自于谷歌翻译 以下为原文 As for BUFGCTRL_XxYy, is the XxYy location coordinates? How to know the XxYy? How can I do the same via GUI? Thank you |
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HI @ dmitry1417
打开合成设计，在网表选项卡中，选择BUGMUX primitve并将其拖动到设备视图中，将其放置在设备中心的BUFG位置。对BUFGCE实例执行相同操作并将其放置在BUFGMUX附近的BUFG位置 location.when保存时，各个LOC约束将写入xdc文件。 ThanksBharath ------------------------------------------------- - --------------------------------------------请标记答案 如果提供的信息可以解决您的疑问/问题，请“接受为解决方案”。给予您认为有用的帖子。感谢.------------------------ -------------------------- ----------- ------------ -------------------- 以上来自于谷歌翻译 以下为原文 HI @dmitry1417 Open synthesized design, In the netlist tab, select the BUGMUX primitve and drag it on the device view , place it some BUFG location at the center of the device. Do the same for the BUFGCE instance and place it on BUFG location adjacent to the BUFGMUX location. when you save , respective LOC constraints will be written into the xdc file. Thanks Bharath ---------------------------------------------------------------------------------------------- Please mark the Answer as "Accept as solution" if information provided addresses your query/concern. Give Kudos to a post which you think is helpful. --------------------------------------------------------------------------------------------- |
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@ dmitry1417，
在Vivado GUI中，您可以使用拖放选项，该选项可以轻松地将实例放置/定位到所需位置。 请查看以下用户指南中的第67页，其中提供了有关实例拖放的详细信息： http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug893-vivado-ide.pdf 保存设计后，将在约束文件中捕获更改。 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @dmitry1417, In Vivado GUI, You can use the drag and drop option which will easily place/loc the instance at desired location. Please check page number 67 in below user guide which gives details on drag and drop of instances: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug893-vivado-ide.pdf Once you save the design then the changes will be captured in constraint file. --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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@ dmitry1417，
如果问题得到解决，请通过标记有助于“接受为解决方案”的帖子来关闭此帖子 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @dmitry1417, If the issue is resolved then please close this thread by marking the post which helped as "Accept as Solution" --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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