如何将RLOC约束应用于生成语句中实例化的fifos？

大家好，
我的设计有一系列的fifo阶段，旨在将来自许多并行处理块的数据汇集到一个fifo中，以便通过光纤接口进行传输。
由于有很多处理块，我想尽可能快地传播数据，因此fifos在第一个字落入模式，每个阶段从2：1减少数据。
我无法满足时序要求，我想尝试根据我在时序结果中看到的内容来应用RLOC约束。
基本上，必须读取两个FIFO，并且必须使用内部数据作出决定的一部分，并立即设置读取启用。
数据有一个时钟要解析并计入下一个fifo。
在时序报告中，最坏情况路径是两个FIFO之间的信号以及读出它们的逻辑。
该设计运行时间为4ns，逻辑延迟约为1.6ns。
在定时失败的情况下，存储器块不会彼此靠近放置，并且路由延迟占总延迟的60％以上。
我知道逻辑能够满足时序，正如许多满足时序的阶段所表明的那样。
FPGA是5LX110T，分别占寄存器和查找表的44％和39％。
我不确定为什么，但在编译期间似乎没有应用我的RLOC约束。
从文档中，我认为我必须应用U_SET约束将两个fifos绑定在一起然后给它们RLOC约束以确保它们彼此相邻。
Y上的5偏移来自PlanAhead设备视图中的tile编号约定。
INST“Uhps_ctp_top / consolidate / gen_stage5 [0] .fifo_inst / U0 / xst_fifo_generator / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.mem / gbm.gbmg.gbmga.ngecc.bmg / gnativebmg.native_blk_mem_gen / valid.cstr / ramloop [0
] .ram.r / v5_noinit.ram / SDP.WIDE_PRIM18.TDP“U_SET = set1;
INST“Uhps_ctp_top / consolidate / gen_stage5 [1] .fifo_inst / U0 / xst_fifo_generator / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.mem / gbm.gbmg.gbmga.ngecc.bmg / gnativebmg.native_blk_mem_gen / valid.cstr / ramloop [0
] .ram.r / v5_noinit.ram / SDP.WIDE_PRIM18.TDP“U_SET = set1;
INST“Uhps_ctp_top / consolidate / gen_stage5 [0] .fifo_inst / U0 / xst_fifo_generator / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.mem / gbm.gbmg.gbmga.ngecc.bmg / gnativebmg.native_blk_mem_gen / valid.cstr / ramloop [0
] .ram.r / v5_noinit.ram / SDP.WIDE_PRIM18.TDP“RLOC = X0Y0;
INST“Uhps_ctp_top / consolidate / gen_stage5 [1] .fifo_inst / U0 / xst_fifo_generator / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.mem / gbm.gbmg.gbmga.ngecc.bmg / gnativebmg.native_blk_mem_gen / valid.cstr / ramloop [0
] .ram.r / v5_noinit.ram / SDP.WIDE_PRIM18.TDP“RLOC = X0Y5;
TL; DR：有谁知道如何将RLOC约束应用于生成语句中实例化的fifos？
谢谢你的期待！
斯科特



以下为原文

Hello everyone,

I've got a design that has a series of fifo stages meant to funnel data from many parallel processing blocks into a single fifo for transmission via a fiber interface.  Since there are so many processing blocks and I'd like to propogate the data as quickly as possible, the fifos are in first word fall through mode and each stage reduces the data from 2:1.

I'm having trouble meeting timing and I'd like to try applying RLOC constraints based on what I'm seeing in the timing results.  Basically, both fifos have to be read and the data inside has to be used to make part of the decision and the read enable is set immediately.  The data has one clock to resolve and be clocked into the next fifo.

In the timing report, the worst case paths are the signals between the two fifos and the logic to read them out.  The design is running at a 4ns period and the logic delay is about 1.6ns.  In cases where timing fails, the memory blocks are not placed close to each other and the routing delays account for more than 60% of the total delay.  I know the logic is capable of meeting timing as indicated by many of the stages meeting timing.  The FPGA is a 5LX110T and is at about 44% and 39% of register and lookup tables, respectively.

I'm not sure why but my RLOC constraints don't seem to be applied during compilation.  From the documentation, I think I have to apply a U_SET constraint to bind the two fifos together and then give them the RLOC constraint to make sure they're placed adjacent to one another.  The 5 offset on Y comes from the Tile numbering convention in the device view of PlanAhead.

INST "Uhps_ctp_top/consolidate/gen_stage5[0].fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP" U_SET=set1;INST "Uhps_ctp_top/consolidate/gen_stage5[1].fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP" U_SET=set1;INST "Uhps_ctp_top/consolidate/gen_stage5[0].fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP" RLOC=X0Y0;INST "Uhps_ctp_top/consolidate/gen_stage5[1].fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP" RLOC=X0Y5;
TL;DR: Does anyone know how to apply RLOC constraints to fifos instantiated in a generate statement?

Thanks for looking!

Scott