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我尝试创建一个包含两个宽多路复用器的两级多路复用器。 每个宽多路复用器具有8个2对1多路复用器,它们共享相同的选择信号。 因为我可以使用RLOC来封装一个宽的多路复用器(= 8个2到1个多路复用器),它们将选择信号共享到一个Virtex-5 Slice中。 我想将这两个宽多路复用器打包成两片。 但是下面的代码给出了一个映射错误:错误:包:679 - 无法遵守设计约束(MACRONAME = hset,RLOC = X2Y2) 有谁知道如何解决这个问题? 模块mux_8(a,c,d,sel,o); 输入[7:0] a; 输入[7:0] d; 输入[7:0] c; 输入[1:0] sel; 输出[7:0] o; 电线[7:0] b; (* RLOC =“X0Y0”*)mux mux_0(.a(a [0]),. b(b [0]),. sesel(sel [0]),. o(o [0])); (* RLOC =“X0Y0”*)mux mux_1(.a(a [1]),. b(b [1]),. sesel(sel [0]),. o(o [1])); (* RLOC =“X0Y0”*)mux mux_2(.a(a [2]),. b(b [2]),. sesel(sel [0]),. o(o [2])); (* RLOC =“X0Y0”*)mux mux_3(.a(a [3]),. b(b [3]),. sesel(sel [0]),. o(o [3])); (* RLOC =“X0Y0”*)mux mux_4(.a(a [4]),. b(b [4]),. sesel(sel [0]),. o(o [4])); (* RLOC =“X0Y0”*)mux mux_5(.a(a [5]),. b(b [5]),. sesel(sel [0]),. o(o [5])); (* RLOC =“X0Y0”*)mux mux_6(.a(a [6]),. b(b [6]),. sesel(sel [0]),. o(o [6])); (* RLOC =“X0Y0”*)mux mux_7(.a(a [7]),. b(b [7]),. sesel(sel [0]),. o(o [7])); (* RLOC =“X2Y2”*)mux mux_8(.a(c [0]),. b(d [0]),. sesel(sel [1]),. o(b [0])); (* RLOC =“X2Y2”*)mux mux_9(.a(c [1]),. b(d [1]),. sesel(sel [1]),. o(b [1])); (* RLOC =“X2Y2”*)mux mux_10(.a(c [2]),. b(d [2]),. sesel(sel [1]),. o(b [2])); (* RLOC =“X2Y2”*)mux mux_11(.a(c [3]),. b(d [3]),. sesel(sel [1]),. o(b [3])); (* RLOC =“X2Y2”*)mux mux_12(.a(c [4]),. b(d [4]),. sesel(sel [1]),. o(b [4])); (* RLOC =“X2Y2”*)mux mux_13(.a(c [5]),. b(d [5]),. sesel(sel [1]),. o(b [5])); (* RLOC =“X2Y2”*)mux mux_14(.a(c [6]),. b(d [6]),. sesel(sel [1]),. o(b [6])); (* RLOC =“X2Y2”*)mux mux_15(.a(c [7]),. b(d [7]),. sesel(sel [1]),. o(b [7])); endmodule(* LUT_MAP =“yes”*)模块mux(a,b,sel,o); 输入a; 输入b; 输入sel; 输出o; 指定o =(~sel& a)| (sel& b); endmodule 以上来自于谷歌翻译 以下为原文 Hi all, I try to create a two level mux which contains two wide muxes. Each wide mux has 8 2-to-1 muxes which share the same select signals. Since I can use RLOC to pack one wide mux (= 8 2-to-1 muxes) which share the select signal into one Virtex-5 slice. I want to pack these two wide muxes into 2 slices. But the following code gives me a map error: ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=hset, RLOC=X2Y2) Anyone know how to solve this? module mux_8(a, c, d, sel, o); input [7:0] a; input [7:0] d; input [7:0] c; input [1:0] sel; output [7:0] o; wire [7:0] b; (* RLOC = "X0Y0" *) mux mux_0(.a(a[0]), .b(b[0]), .sel(sel[0]), .o(o[0])); (* RLOC = "X0Y0" *) mux mux_1(.a(a[1]), .b(b[1]), .sel(sel[0]), .o(o[1])); (* RLOC = "X0Y0" *) mux mux_2(.a(a[2]), .b(b[2]), .sel(sel[0]), .o(o[2])); (* RLOC = "X0Y0" *) mux mux_3(.a(a[3]), .b(b[3]), .sel(sel[0]), .o(o[3])); (* RLOC = "X0Y0" *) mux mux_4(.a(a[4]), .b(b[4]), .sel(sel[0]), .o(o[4])); (* RLOC = "X0Y0" *) mux mux_5(.a(a[5]), .b(b[5]), .sel(sel[0]), .o(o[5])); (* RLOC = "X0Y0" *) mux mux_6(.a(a[6]), .b(b[6]), .sel(sel[0]), .o(o[6])); (* RLOC = "X0Y0" *) mux mux_7(.a(a[7]), .b(b[7]), .sel(sel[0]), .o(o[7])); (* RLOC = "X2Y2" *) mux mux_8 (.a(c[0]), .b(d[0]), .sel(sel[1]), .o(b[0])); (* RLOC = "X2Y2" *) mux mux_9 (.a(c[1]), .b(d[1]), .sel(sel[1]), .o(b[1])); (* RLOC = "X2Y2" *) mux mux_10(.a(c[2]), .b(d[2]), .sel(sel[1]), .o(b[2])); (* RLOC = "X2Y2" *) mux mux_11(.a(c[3]), .b(d[3]), .sel(sel[1]), .o(b[3])); (* RLOC = "X2Y2" *) mux mux_12(.a(c[4]), .b(d[4]), .sel(sel[1]), .o(b[4])); (* RLOC = "X2Y2" *) mux mux_13(.a(c[5]), .b(d[5]), .sel(sel[1]), .o(b[5])); (* RLOC = "X2Y2" *) mux mux_14(.a(c[6]), .b(d[6]), .sel(sel[1]), .o(b[6])); (* RLOC = "X2Y2" *) mux mux_15(.a(c[7]), .b(d[7]), .sel(sel[1]), .o(b[7])); endmodule (* LUT_MAP = "yes" *) module mux(a, b, sel, o); input a; input b; input sel; output o; assign o = (~sel & a) | (sel & b); endmodule |
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你没有发布整个Pack:679错误。
除列出所涉及的约束外,它还列出了所涉及的所有实例,并提供了描述无法遵守约束的原因的摘要。 它是否抱怨连接问题? 检查您是否在每种情况下使用正确的MUX输入引脚以使电池组正常工作。 以上来自于谷歌翻译 以下为原文 You didn't post the entire Pack:679 error. Besides listing the constraint involved, it also lists all instances involved and provides a summary describing why the constraint could not be obeyed. Is it complaining about a connectivity issue? Check to see that you are using the correct MUX input pin in each case for the pack to work. |
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嗨,
我粘贴下面的详细错误消息。 我无法完全理解这个消息。 请给我一些提示。 谢谢! 使用目标部件“5vlx330tff1738-2”。将设计映射到LUT ...运行定向打包...错误:包装:679 - 无法遵守设计约束(MACRONAME = hset,RLOC = X2Y2),这需要组合以下符号 到单个SLICE组件:LUT符号“mux_0”(输出信号= o_0_OBUF)LUT符号“mux_1”(输出信号= o_1_OBUF)LUT符号“mux_2”(输出信号= o_2_OBUF)LUT符号“mux_3”(输出信号= o_3_OBUF) LUT符号“mux_4”(输出信号= o_4_OBUF)LUT符号“mux_5”(输出信号= o_5_OBUF)LUT符号“mux_6”(输出信号= o_6_OBUF)LUT符号“mux_7”(输出信号= o_7_OBUF)发现函数发生器 有不兼容的输入信号。 请相应地更正设计约束。完成填充。有关详细信息,请参阅MAP报告文件“mux_8_map.mrp”。在打包阶段遇到问题。 以上来自于谷歌翻译 以下为原文 Hi, I paste the detail error message below. I could not understand the message completely. Please give me some hints. Thank you! Using target part "5vlx330tff1738-2". Mapping design into LUTs... Running directed packing... ERROR: Pack:679 - Unable to obey design constraints (MACRONAME=hset, RLOC=X2Y2) which require the combination of the following symbols into a single SLICE component: LUT symbol "mux_0" (Output Signal = o_0_OBUF) LUT symbol "mux_1" (Output Signal = o_1_OBUF) LUT symbol "mux_2" (Output Signal = o_2_OBUF) LUT symbol "mux_3" (Output Signal = o_3_OBUF) LUT symbol "mux_4" (Output Signal = o_4_OBUF) LUT symbol "mux_5" (Output Signal = o_5_OBUF) LUT symbol "mux_6" (Output Signal = o_6_OBUF) LUT symbol "mux_7" (Output Signal = o_7_OBUF) The function generators were found to have incompatible input signals. Please correct the design constraints accordingly. Mapping completed. See MAP report file "mux_8_map.mrp" for details. Problem encountered during the packing phase. |
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切片中的8个LUT将需要在所有4个LUT复合体中进行LUT组合(每个切片2个LUT),并且需要2个组合LUT之间的共享信号连接。
这就是Pack:679错误所抱怨的。 以上来自于谷歌翻译 以下为原文 Eight LUTs in a slice will require LUT combining (2 LUTs per slice) in all 4 LUT complexes and that requires shared signal connectivity between the 2 combined LUTs. That's what the Pack:679 error is complaining about. |
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现在,我已经运行了测试用例,我发现设计应该按原样运行。
我能够通过添加一些LUT结合约束来指导打包来使其工作。 这很奇怪,因为所有LUT都是LUT3,有一个共享输入,因此所有LUT都有资格与其他任何一个组合。 我怀疑我的约束阻止了LUT优化,这种优化破坏了无约束(来自LUT组合POV)包。 INST“mux_0”LUTNM = LP0; INST“mux_1”LUTNM = LP0; INST“mux_2”LUTNM = LP1; INST“mux_3”LUTNM = LP1; INST“mux_4”LUTNM = LP2; INST“mux_5”LUTNM = LP2; INST“ mux_6“LUTNM = LP3; INST”mux_7“LUTNM = LP3; 以上来自于谷歌翻译 以下为原文 Now, that I've run the test case I see that the design should have worked as it is. I was able to get it to work by adding some LUT combining constraints to guide the packing. This is odd since all of the LUTs were LUT3s with one shared input and so all should have been eligible to be combined with any other. I suspect that my constraints blocked a LUT optimization that was breaking the unconstrained (from LUT combining POV) pack. INST "mux_0" LUTNM = LP0; INST "mux_1" LUTNM = LP0; INST "mux_2" LUTNM = LP1; INST "mux_3" LUTNM = LP1; INST "mux_4" LUTNM = LP2; INST "mux_5" LUTNM = LP2; INST "mux_6" LUTNM = LP3; INST "mux_7" LUTNM = LP3; |
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嗨bwade,
对于迟到的回复抱歉! 我还有一个问题。 在我阅读Xilinx关于LUTNM的约束指南之后,我理解我们可以使用它来将实例分组到物理资源。 我的问题是以下约束: INST“mux_0”LUTNM = LP0; 1.什么是LP0? 2. LP1与LP0有任何关联吗? 谢谢! 以上来自于谷歌翻译 以下为原文 Hi bwade, Sorry about the late reply! I still have one more question. After I read the constraint guide from Xilinx about LUTNM, I understand that we can use it to group instances to physical resources. My question is for the following constraint: INST "mux_0" LUTNM = LP0; 1. What is LP0? 2. Does LP1 have any correlation with LP0? Thank you! |
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LP0只是我分配给LUT对的任意名称。
以上来自于谷歌翻译 以下为原文 LP0 was just an arbitrary name that I assigned to the LUT pair. |
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刚刚提出了另外两个相关的两个问题:
1.我添加的RLOC约束怎么样? 我认为RLOC已经完成了将4个多路复用器打包成一片的工作。 这两个约束如何相互作用? 对于我只有8个多路复用器(共享选择信号)的另一个例子,我可以使用RLOC将它们打包成1个切片。 但是删除RLOC约束并且仅放置LUTNM约束,结果是使用4个切片。 所以我真的很担心LUTNM的目的。 2.什么是LUT对? 我只在Xilinx软件中看到术语LUT-FF对。 为什么我需要指定哪个mux映射到哪个LUT对? 以上来自于谷歌翻译 以下为原文 Just came up with another related two questions: 1. What about the RLOC constraint I add? I thought RLOC already did the job to pack 4 muxes into one slices. How does these two constraints interact with each other? For another example in which I only have 8 muxes (share select signals), I can use RLOC to pack them into 1 slice. But remove the RLOC constraint and only put the LUTNM constraint, it turns out to use 4 slices. So I am really confuse about the purpose of LUTNM. 2. What is a LUT pair? I only see the term LUT-FF pair in Xilinx software. Why do I need to specify which mux maps to which LUT pair? |
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我在一个切片中打包了8个多路复用器,并在需要时实例化它。
它解决了这个问题。 以上来自于谷歌翻译 以下为原文 I packed 8 muxes in one slice and instantiate it whenever I need it. It solves the problem. |
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