Place＆Route后引脚约束发生了变化

##########################################################################
##############################由Xilinx EDK的基本系统生成器向导创建13.1构建EDK_O.40d #Sat Feb 25 25：
2012年5月52日＃目标板：Xilinx Virtex 5 ML507评估平台版本A＃系列：virtex5＃器件：xc5vfx70t＃封装：ff1136＃速度等级：-1＃处理器编号：1＃处理器1：ppc440_0＃处理器时钟频率：400.0＃
总线时钟频率：100.0＃调试接口：FPGA JTAG #######################################
########################################参数版本= 2.1.0
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin，DIR = IPORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin，DIR = OPORT fpga_0_clk_1_sys_clk_pin = CLK_S，DIR = I，SIGIS = CLK，CLK_FREQ = 100000000PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s，DIR = I，SIGIS = RST，RST_POLARITY = 0PORT hdlc_core_0_tp0_pin = hdlc_core_0_tp0，DIR
= OPORT hdlc_core_0_tp1_pin = hdlc_core_0_tp1，DIR = O
BEGIN ppc440_virtex5PARAMETER INSTANCE = ppc440_0PARAMETER C_IDCR_BASEADDR = 0b0000000000PARAMETER C_IDCR_HIGHADDR = 0b0011111111PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 0PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0PARAMETER HW_VER = 1.01.aBUS_INTERFACE MPLB = plb_v46_0BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_busBUS_INTERFACE RESETPPC = ppc_reset_busPORT CPMC440CLK = clk_400_0000MHzPLL0PORT CPMINTERCONNECTCLK = clk_200_0000MHzPLL0PORT CPMINTERCONNECTCLKNTO1 = net_vccPORT CPMMCCLK = clk_100_0000MHzPLL0_ADJUSTEND
BEGIN plb_v46PARAMETER INSTANCE = plb_v46_0PARAMETER C_DCR_INTFCE = 0PARAMETER HW_VER = 1.05.aPORT PLB_Clk = clk_100_0000MHzPLL0_ADJUSTPORT SYS_Rst = sys_bus_resetEND
BEGIN xps_bram_if_cntlrPARAMETER INSTANCE = xps_bram_if_cntlr_1PARAMETER C_SPLB_NATIVE_DWIDTH = 64PARAMETER C_SPLB_SUPPORT_BURSTS = 1PARAMETER C_SPLB_P2P = 0PARAMETER HW_VER = 1.00.bPARAMETER C_BASEADDR = 0xffffe000PARAMETER C_HIGHADDR = 0xffffffffBUS_INTERFACE SPLB = plb_v46_0BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_portEND
BEGIN bram_blockPARAMETER INSTANCE = xps_bram_if_cntlr_1_bramPARAMETER HW_VER = 1.00.aBUS_INTERFACE PORTA = xps_bram_if_cntlr_1_portEND
BEGIN xps_uartlitePARAMETER INSTANCE = RS232_Uart_1PARAMETER C_BAUDRATE = 9600PARAMETER C_DATA_BITS = 8PARAMETER C_USE_PARITY = 0PARAMETER C_ODD_PARITY = 0PARAMETER HW_VER = 1.01.aPARAMETER C_BASEADDR = 0x84000000PARAMETER C_HIGHADDR = 0x8400ffffBUS_INTERFACE SPLB = plb_v46_0PORT RX = fpga_0_RS232_Uart_1_RX_pinPORT TX = fpga_0_RS232_Uart_1_TX_pinEND
BEGIN clock_generatorPARAMETER INSTANCE = clock_generator_0PARAMETER C_CLKIN_FREQ = 100000000PARAMETER C_CLKOUT0_FREQ = 100000000PARAMETER C_CLKOUT0_PHASE = 0PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUSTPARAMETER C_CLKOUT0_BUF = TRUEPARAMETER C_CLKOUT1_FREQ = 200000000PARAMETER C_CLKOUT1_PHASE = 0PARAMETER C_CLKOUT1_GROUP = PLL0PARAMETER C_CLKOUT1_BUF = TRUEPARAMETER C_CLKOUT2_FREQ = 400000000PARAMETER C_CLKOUT2_PHASE = 0PARAMETER C_CLKOUT2_GROUP = PLL0PARAMETER C_CLKOUT2_BUF = TRUEPARAMETER C_EXT_RESET_HIGH = 0PARAMETER HW_VER = 4.01
.aPORT CLKIN = CLK_SPORT CLKOUT0 = clk_100_0000MHzPLL0_ADJUSTPORT CLKOUT1 = clk_200_0000MHzPLL0PORT CLKOUT2 = clk_400_0000MHzPLL0PORT RST = sys_rst_sPORT LOCKED = Dcm_all_lockedEND
BEGIN jtagppc_cntlrPARAMETER INSTANCE = jtagppc_cntlr_instPARAMETER HW_VER = 2.01.cBUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_busEND
BEGIN proc_sys_resetPARAMETER INSTANCE = proc_sys_reset_0PARAMETER C_EXT_RESET_HIGH = 0PARAMETER HW_VER = 3.00.aBUS_INTERFACE RESETPPC0 = ppc_reset_busPORT Slowest_sync_clk = clk_100_0000MHzPLL0_ADJUSTPORT Ext_Reset_In = sys_rst_sPORT Dcm_locked = Dcm_all_lockedPORT Bus_Struct_Reset = sys_bus_resetPORT Peripheral_Reset = sys_periph_resetEND
BEGIN hdlc_corePARAMETER INSTANCE = hdlc_core_0PARAMETER HW_VER = 1.00.aPARAMETER C_MEM0_BASEADDR = 0x60000000PARAMETER C_MEM0_HIGHADDR = 0x6000FFFFBUS_INTERFACE SPLB = plb_v46_0PORT tp0 = hdlc_core_0_tp0PORT tp1 = hdlc_core_0_tp1END



以下为原文


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.1 Build EDK_O.40d
# Sat Feb 25 09:05:52 2012
# Target Board:  Xilinx Virtex 5 ML507 Evaluation Platform Rev A
# Family:    virtex5
# Device:    xc5vfx70t
# Package:   ff1136
# Speed Grade:  -1
# Processor number: 1
# Processor 1: ppc440_0
# Processor clock frequency: 400.0
# Bus clock frequency: 100.0
# Debug Interface: FPGA JTAG
# ##############################################################################
 PARAMETER VERSION = 2.1.0

 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
 PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
 PORT hdlc_core_0_tp0_pin = hdlc_core_0_tp0, DIR = O
 PORT hdlc_core_0_tp1_pin = hdlc_core_0_tp1, DIR = O

BEGIN ppc440_virtex5
 PARAMETER INSTANCE = ppc440_0
 PARAMETER C_IDCR_BASEADDR = 0b0000000000
 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
 PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 0
 PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
 PARAMETER HW_VER = 1.01.a
 BUS_INTERFACE MPLB = plb_v46_0
 BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 PORT CPMC440CLK = clk_400_0000MHzPLL0
 PORT CPMINTERCONNECTCLK = clk_200_0000MHzPLL0
 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
 PORT CPMMCCLK = clk_100_0000MHzPLL0_ADJUST
END
BEGIN plb_v46
 PARAMETER INSTANCE = plb_v46_0
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER HW_VER = 1.05.a
 PORT PLB_Clk = clk_100_0000MHzPLL0_ADJUST
 PORT SYS_Rst = sys_bus_reset
END
BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
 PARAMETER C_SPLB_SUPPORT_BURSTS = 1
 PARAMETER C_SPLB_P2P = 0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0xffffe000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT RX = fpga_0_RS232_Uart_1_RX_pin
 PORT TX = fpga_0_RS232_Uart_1_TX_pin
END
BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 400000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = PLL0
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 4.01.a
 PORT CLKIN = CLK_S
 PORT CLKOUT0 = clk_100_0000MHzPLL0_ADJUST
 PORT CLKOUT1 = clk_200_0000MHzPLL0
 PORT CLKOUT2 = clk_400_0000MHzPLL0
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
END
BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_cntlr_inst
 PARAMETER HW_VER = 2.01.c
 BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
END
BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 3.00.a
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
 PORT Slowest_sync_clk = clk_100_0000MHzPLL0_ADJUST
 PORT Ext_Reset_In = sys_rst_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END
BEGIN hdlc_core
 PARAMETER INSTANCE = hdlc_core_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MEM0_BASEADDR = 0x60000000
 PARAMETER C_MEM0_HIGHADDR = 0x6000FFFF
 BUS_INTERFACE SPLB = plb_v46_0
 PORT tp0 = hdlc_core_0_tp0
 PORT tp1 = hdlc_core_0_tp1
END

#Virtex 5 ML507评估平台网络fpga_0_RS232_Uart_1_RX_pin LOC = AG15 |
IOSTANDARD = LVCMOS33; Net fpga_0_RS232_Uart_1_TX_pin LOC = AG20 |
IOSTANDARD = LVCMOS33; Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin; TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz; Net fpga_0_clk_1_sys_clk_pin LOC = AH15 |
IOSTANDARD = LVCMOS33; Net fpga_0_rst_1_sys_rst_pin TIG; Net fpga_0_rst_1_sys_rst_pin LOC = E9 |
IOSTANDARD = LVCMOS33 |
PULLUP;＃由wuxianNET添加hdlc_core_0_tp0_pin LOC = H33;
＃HDR1_2 for ML507NET hdlc_core_0_tp1_pin LOC = F34;
ML507的＃HDR1_4



以下为原文

#  Virtex 5 ML507 Evaluation Platform
Net fpga_0_RS232_Uart_1_RX_pin LOC = AG15  |  IOSTANDARD=LVCMOS33;
Net fpga_0_RS232_Uart_1_TX_pin LOC = AG20  |  IOSTANDARD=LVCMOS33;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC = AH15  |  IOSTANDARD=LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC = E9  |  IOSTANDARD=LVCMOS33  |  PULLUP;
# added by wuxian
NET hdlc_core_0_tp0_pin LOC = H33; # HDR1_2 for ML507
NET hdlc_core_0_tp1_pin LOC = F34; # HDR1_4 for ML507

#hdlc_core_embedd_top.lpc＃此文件中的约束只是为了查看而创建的。
＃如果您希望使用这些约束，请将它们复制到#project的约束文件中。
如果您还没有项目约束#file，请使用“Project-> New Source”菜单创建一个。
#pin2ucf  -  Sat Feb 25 09:56:31 2012＃新添加了以下约束“fpga_0_clk_1_sys_clk_pin”LOC = AH15; NET“fpga_0_RS232_Uart_1_RX_pin”LOC = AG15; NET“hdlc_core_0_tp0_pin”LOC = F34; NET“fpga_0_rst_1_sys_rst_pin”LOC = E9;
NET“hdlc_core_0_tp1_pin”LOC = T33; NET“fpga_0_RS232_Uart_1_TX_pin”LOC = AG20;



以下为原文

# hdlc_core_embedd_top.lpc 
#   The constraints in this file were created simply to be viewed. 
#   If you wish to use these constraints, please copy them into your 
#   project's constraint file. If you do not have a project constraints 
#   file yet, please use the "Project->New Source" menu to create one.
 
#pin2ucf - Sat Feb 25 09:56:31 2012
#The following constraints were newly added
NET "fpga_0_clk_1_sys_clk_pin" LOC = AH15;
NET "fpga_0_RS232_Uart_1_RX_pin" LOC = AG15;
NET "hdlc_core_0_tp0_pin" LOC = F34;
NET "fpga_0_rst_1_sys_rst_pin" LOC = E9;
NET "hdlc_core_0_tp1_pin" LOC = T33;
NET "fpga_0_RS232_Uart_1_TX_pin" LOC = AG20;

hdlc_core_v2_1_0.mpd
## PortsPORT tp0 =“”，DIR = O＃由wuxianPORT添加tp1 =“”，DIR = O＃由wuxian添加
hdlc_core.vhd
...
实体hdlc_core是
...
端口（ - 在此线路下方添加用户端口------------------  - 此处添加了用户端口 - 在此线路上添加用户端口--------
---------- tp0：out std_logic;  - 由wuxian tp1添加：out std_logic;  - 由wuxian添加 - 请勿编辑此行以下------------
---------
...
组件user_logic是
...
端口（ - 添加此线路以下的用户端口------------------  - 这里添加的用户端口tp0：out std_logic;  - 由wuxian tp1添加：out std_logic;  -
- 由wuxian添加 - 在此线路上添加用户端口------------------
...
USER_LOGIC_I：组件user_logic
...
端口映射（ - 本行以下的MAP用户端口------------------  - 这里映射的用户端口tp0 => tp0， - 由wuxian tp1 => tp1添加，
- 由wuxian添加 -  MAP用户端口在此线路上------------------
...
.user_logic.v
module user_logic（//  - 在此行之后添加用户端口--------------- //  - 此处添加的用户端口tp0，//由wuxian添加，测试点0 tp1，/
/由wuxian添加，测试点1 //  - 在此线路上添加用户端口---------------
...
//  - 在此行之外添加用户端口----------------- //  - 在此处输入的输出端口tp0;
//由wuxianoutput tp1添加;
//由wuxian添加
... 
//  - 此处添加的USER逻辑实现指定tp0 = 1'b1;
//由wuxian添加tp1 = 1'b1;
//由wuxian添加
...



以下为原文

hdlc_core_v2_1_0.mpd
## Ports
PORT tp0 = "", DIR = O # added by wuxian
PORT tp1 = "", DIR = O # added by wuxian
 
hdlc_core.vhd
...
entity hdlc_core is
...
port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
    -- ADD USER PORTS ABOVE THIS LINE ------------------
    tp0                         : out std_logic; -- added by wuxian
    tp1                         : out std_logic; -- added by wuxian
    -- DO NOT EDIT BELOW THIS LINE ---------------------
...
component user_logic is
...
port
    (
      -- ADD USER PORTS BELOW THIS LINE ------------------
      --USER ports added here
      tp0                           : out std_logic; -- added by wuxian
      tp1                           : out std_logic; -- added by wuxian
      -- ADD USER PORTS ABOVE THIS LINE ------------------
...
 USER_LOGIC_I : component user_logic
...
port map
    (
      -- MAP USER PORTS BELOW THIS LINE ------------------
      --USER ports mapped here
      tp0                           => tp0, -- added by wuxian
      tp1                           => tp1, -- added by wuxian
      -- MAP USER PORTS ABOVE THIS LINE ------------------
...
 
 
.user_logic.v
module user_logic
(
  // -- ADD USER PORTS BELOW THIS LINE ---------------
  // --USER ports added here
  tp0, // added by wuxian, test point 0
  tp1, // added by wuxian, test point 1
  // -- ADD USER PORTS ABOVE THIS LINE ---------------
...
// -- ADD USER PORTS BELOW THIS LINE -----------------
// --USER ports added here
output tp0; // added by wuxian
output tp1; // added by wuxian
...
  // --USER logic implementation added here
    assign tp0 = 1'b1; // added by wuxian
    assign tp1 = 1'b1; // added by wuxian
...