时钟引脚的错误

嗨@asmabdg
欢迎来到论坛！
正如您所怀疑的那样，您收到的错误通常意味着使用不具有时钟功能的引脚将时钟连接到FPGA。
- 你再次说这些引脚被称为MRCC和SRCC引脚是正确的。
在Zynq-7030 FPGA中，您可以找到使用Xilinx文档ug865的时钟引脚的位置。
干杯，
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以下为原文

Hi @asmabdg
 
Welcome to the Forum!
 
As you suspect, the error you received usually means that a clock is being brought into the FPGA using pin(s) that are not clock-capable.  -and you are again correct in saying that these pins are called MRCC and SRCC pins.  For the Zynq-7030 FPGA, you will find the location of the clock-capable pins using Xilinx document, ug865, that is located .
 
Cheers,
Mark

@asmabdg，
如上所述，确保yourIO具备时钟功能。
如果它具有时钟功能，则打开合成设计并运行以下命令：
opt_design
place_ports
这会运行I / O和时钟放置，并留下部分放置的设计用于调查。
“place_ports”可能会报告错误，但您仍然可以查看部分展示位置。
现在搜索错误消息中提到的IO端口和MMCM。
如果它们不在同一时钟区域，则可能发生错误。
--Syed
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以下为原文

@asmabdg,
 
As mentioned above, make sure your IO is clock capable. If it is clock capable then Open the synthesized design and run the following commands:
opt_design
place_ports
 
This runs I/O and clock placement and leaves the partially placed design for investigation. "place_ports" might report an error but you can still view the partial placement.
 
Now search the IO port and MMCM mentioned in error message. The error could happen if they are not in same clock region.
 
--Syed
 
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@asmabdg
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--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@asmabdg
 
Any update on this forum thread? Let us know if you have any more queries. 
If the issue is resolved then please close this thread by marking the helpful post as "Accept as Solution"
 
--Syed
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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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