时钟限制和双向IO有哪些其他用例？

1）clock dedicated route = false  - 我们什么时候应该使用这个约束？
我知道这个约束的功能 - 如果你需要将一些时钟引脚放在违反时钟规则的IOB片上，那么在ucf中将此参数设置为false。
但除此之外，这种约束还有哪些其他用例？
如果我有一个来自gpio引脚的i2c时钟并进入我的设计，那么我应该将此路径设置为clock_dedicated_route = false具体还是我应该等待查看该工具吐出的内容？
我们应该将此约束用于慢速/快速时钟吗？
它有助于满足时机或改善它吗？
答：工具对时钟施加了某些规则，以确保工具容易满足时序，并且没有违规。
不只是这个，而是来自用户指南的其他时钟规则如果被忽略可能会引起问题。
您应该等待该工具抛出这些错误。
你不应该直接在UCF中分配这个约束。
但是，您应该确定要提供此约束，因为xilinx建议遵循时钟规则。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

1) clock dedicated route = false - when should we use this constraint? i know the function of this constraint - if you need to place some clock pins an an IOB slice which violates clocking rules, then set this parameter to false in ucf. but other than that, what other use case will this constraint have?
 
if i have an i2c clock coming from a gpio pin and going into my design, then should i set this path to clock_dedicated_route = false specifically or should i wait to see what the tool spits out? 
 
should we use this constraint for slow/fast clocks?
 
will it help in meeting timing or disimprove it? 
A: There are certain rules which the tool imposes on the clocks to make sure that the timing is met easily for the tool and there are no violations. Not just this but other clocking rules from the user guide which if ignored may cause problems are noted. You should wait for the tool to throw these errors. YOu should not directly assign this constraint in UCF. 
 
However you should be sure that you want to give this constraint because mostly, the xilinx recommendation is to follow the clocking rules.
 
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

2）这可能更像是一个noob问题 - 我们是否应该通过gpio引脚限制进入我们设计的时钟（引脚不会进入PLL而是在设计中为模块提供时钟）？
如果以上是肯定的，那么除了期间约束外，是否还有任何其他建议的约束应该使用，除了期间收敛？
答：是的，即使没有PLL或任何时钟管理器，您也应该给出时序约束。
是PERIOD约束应该足够的时钟。
但是，对于某些交叉时钟路径和IO（不是时钟而是数据IO），还需要其他时序约束。
你需要检查UG360的时间信息..
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

2)this may be a bit more of a noob question - should we constraint clocks that go into our design via a gpio pin (the pin does not go into a PLL but clocks modules within the design)?
 
if the above is yes, then apart from period constraint, are there any other recommended constraints that should be used, apart from period constriant?
 
A: yes even without a PLL or any clock manager, you SHOULD give the timing constraints. Yes PERIOD constraint should be enough for the clock. however there are other timing constraints which are needed for certain cross clock paths and for the IO's(not clock but data IO's). YOu need to check UG360 for the information on the timing..
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

嗨，
3）如果有一个时钟通过gpio引脚从我的设计中消失，那么我应该约束它吗？
如果是，只有周期约束或是否有任何其他建议的约束？
答：对于一个走出设计的时钟，我认为你不需要约束。
PERIOD约束仅适用于具有结构的同步元素之间的逻辑传输。
如果在内部使用该时钟，则需要周期约束。
如果您直接尝试输出时钟，则无法给出PERIOD约束。
但是，对于FPGA和连接组件之间的源同步接口，您需要处理连接组件的时序。
对于IO时序，您需要更多地关注数据引脚，并且需要使用OFFSE_OUT来限制数据引脚相对于锁存时钟，而不是限制时钟。
这有道理吗？
阅读UG360，了解时间限制的清晰度。
4）如果我将gpio引脚声明为输入，并且仅将其连接到我设计中的一个子模块的输出引脚（或输入引脚），那么我是否还需要一个三态缓冲器来处理bi-
dir IO？
或者xilinx会自行解析吗？
答：你需要一个三态缓冲区。
检查库指南中的thetristate buffer module。
但在此之前，我建议你实现这个，并检查该工具推断出什么。
但是实例化更安全。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi,
 
3) if there is a clock that goes out of my design via a gpio pin, then should i constrain it? if yes, only period constraint or are there any other recommended constraints?
A: For a clock going out of the design, i dont think you need a constraint. The PERIOD constraint is only for the logic transfer between synchronous elements withing the fabric. If that clock is being used internally then that needs period constraint. If you are directly trying to output the clock, there is no use giving a PERIOD constraint. However for source synchronous interfaces between the FPGA and the connected component, you need to take care of the timing at the connected component.
 
For IO timing you need to focus more on the data pins and you would need to constraint the data pins using OFFSE_OUT with respect to the latching clock, rather than constraint the clock. Does this makes sense? Read through UG360 for clarity on the timign constraints.
 
4) if i declare a gpio pin as inout, and only connect it to a an output pin (or input pin) from one of the sub-modules in my design, then do i still need a tri-state buffer to handle bi-dir IO? or will xilinx reslolve it itself?
A:You would need a tri-state buffer. Check the library guide for the tristate buffer module. However before that i would recommend you to implement this and check what does the tool infer. However it is safer to instantiate.
 
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

嗨，关于Q.1我建议尽量避免使用clock dedicated route = false约束。
尝试实现有效的时钟结构。
如果不能使用专用时钟路由，那么你可以使用这个约束。这个时钟专用route = false约束的缺点。
PVT变化会影响时钟偏差的更多结果。谢谢，Yash



以下为原文

Hi,

Regarding Q.1 I will suggest try to avoid as much as possible to use clock dedicated route = false constraints. Try to achieve valid clocking structure. If in case it's impossible to use dedicated clock routing then you can use this constraints.

There are draw backs of this  clock dedicated route = false constraints. PVT variation affects more results in clock skew.

Thanks,
Yash

嗨@ zubin_kumar31
如果有帮助，请将此主题关闭为“Accept as Solution”。
谢谢，Anirudh
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi @zubin_kumar31 

Please close this thread as "Accept as Solution" in case it helped.

Thanks,
Anirudh
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

zubin_kumar31写道：
喜
我有一些关于时钟限制和bi-dir gpios的问题 -
1）clock dedicated route = false  - 我们什么时候应该使用这个约束？
我知道这个约束的功能 - 如果你需要将一些时钟引脚放在违反时钟规则的IOB片上，那么在ucf中将此参数设置为false。
但除此之外，这种约束还有哪些其他用例？
当您（无意中，通常在极少数情况下故意）将时钟输入信号放入非时钟/全局时钟输入引脚时，您可以使用它。
但要注意。
如果您这样做，则无法保证您将满足输入设置和保留要求。
换句话说，应尽可能避免。
如果我有一个来自gpio引脚的i2c时钟并进入我的设计，那么我应该将此路径设置为clock_dedicated_route = false具体还是我应该等待查看该工具吐出的内容？
专业提示：I2C时钟信号SCL实际上不是标准使用的时钟。
你应该做的是把它带到你想要的任何引脚上，并用你的系统时钟对它进行过采样以找到边缘。
我们应该将此约束用于慢速/快速时钟吗？
什么是“慢”或“快”时钟？
随你。
该约束仅用于如上所述。
它有助于满足时机或改善它吗？
当你搞砸PCB布局时，它可以帮助路由器完成它的工作，但通常你不会遇到一些时间。
2）这可能更像是一个noob问题 - 我们是否应该通过gpio引脚限制进入我们设计的时钟（引脚不会进入PLL而是在设计中为模块提供时钟）？
时钟必须始终受到约束。
通常，您在时钟输入上放置PERIOD约束。
如果该时钟馈送PLL或DLL，则工具会为这些资源生成的时钟创建约束。
如果以上是肯定的，那么除了期间约束外，是否还有任何其他建议的约束应该使用，除了期间收敛？
对于与这些时钟同步的输入，应创建OFFSET IN约束，以确保满足设置和保持时间。
3）如果有一个时钟通过gpio引脚从我的设计中消失，那么我应该约束它吗？
如果是，只有周期约束或是否有任何其他建议的约束？
你没有。
如果创建源同步输出总线（各种数据位与该输出时钟同步），则应对数据和时钟引脚创建OFFSET OUT约束（参考生成输出时钟的输入时钟）并查找
偏差。
4）如果我将gpio引脚声明为输入，并且仅将其连接到我设计中的一个子模块的输出引脚（或输入引脚），那么我是否还需要一个三态缓冲器来处理bi-
dir IO？
或者xilinx会自行解析吗？
这些工具可能会发出警告。
不要那样做。
将引脚声明为输入或输出。
如果您决定更改文件，则稍后编辑该文件并不困难。
----------------------------是的，我这样做是为了谋生。



以下为原文

zubin_kumar31 wrote:
hi,
i had some questions regarding clock constraints and  bi-dir gpios -
1) clock dedicated route = false - when should we use this constraint? i know the function of this constraint - if you need to place some clock pins an an IOB slice which violates clocking rules, then set this parameter to false in ucf. but other than that, what other use case will this constraint have?

You use it when you (inadvertenly, usually, but on rare occasions deliberately) put a clock input signal onto a non-clock-capable/global clock input pin. But be warned. If you do that, there are no guarantees that you'll meet input setup and hold requirements.
 
In other words, it is to be avoided as much as possible.

if i have an i2c clock coming from a gpio pin and going into my design, then should i set this path to clock_dedicated_route = false specifically or should i wait to see what the tool spits out? 

Pro Tip: the I2C clock signal SCL really isn't a clock in the standard usage. What you should do is bring it in on any pin you wish, and oversample it with your system clock to find the edge.

should we use this constraint for slow/fast clocks?

What is a "slow" or "fast" clock?
Whatever. That constraint is only used as described above.

will it help in meeting timing or disimprove it?

It helps the router complete its job when you screw up the PCB layout, but in general you won't meet some timing.

2)this may be a bit more of a noob question - should we constraint clocks that go into our design via a gpio pin (the pin does not go into a PLL but clocks modules within the design)?

Clocks must always be constrained. Generally, you place a PERIOD constraint on the clock input. If that clock feeds a PLL or DLL, the tools with create constraints for the clocks generated by those resources.

if the above is yes, then apart from period constraint, are there any other recommended constraints that should be used, apart from period constriant?

For inputs synchronous to those clocks, you should create an OFFSET IN constraint, to ensure that you meet setup and hold times.

3) if there is a clock that goes out of my design via a gpio pin, then should i constrain it? if yes, only period constraint or are there any other recommended constraints?

You don't. If you create a source-synchronous output bus (with various data bits synchronous to that output clock), you should create OFFSET OUT constraints on the data and the clock pin (with reference to the input clock which generates the output clock) and look for skew differences.

4) if i declare a gpio pin as inout, and only connect it to a an output pin (or input pin) from one of the sub-modules in my design, then do i still need a tri-state buffer to handle bi-dir IO? or will xilinx reslolve it itself?

The tools will probably throw a warning. Don't do that. Declare the pin as an input or an output. It's not hard to edit the file later if you decide to change it.
----------------------------Yes, I do this for a living.