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我需要产生一组视频像素时钟--27 MHz,74.25,148.5 MHz,297 MHz,并且每个Clk速率从Clk切换到Clk / 1.001。
在之前的项目中(Spartan 3 - 限制为148.5 MHz max Clk)我使用单个DCM从两个外部时钟(74.25 MHz和74.25 / 1.001 MHz)产生所有必需的Clk速率。 对于一个新项目,我使用的是Spartan 6,并且想考虑使用单个外部时钟来获得Clk和Clk / 1.001速率,但这需要一长串DCM和PLL。 特别, 27 MHz外部CLk - > DCM0 - > DCM1 - > PLL0产生74.25 MHz和74.25 / 1.001 MHz时钟。 然后 74.25 MHz和74.25 / 1.001 MHz时钟 - > PLL1产生所有必需的视频clks。 时钟向导将每个DCM / PLL的单个抖动报告为 DCM0 - 213 ps,DCM1 - 221 ps,PLL0 - 182 ps,PLL1 - 158 ps 任何人都可以建议我是否可以期待这个2 DCM& 2 PLL链可用于视频吗? 我是否期望抖动是4个分量(390 ps)的平方和的平方根? 或者在级联结束时使用PLL来清除先前PLL和放大器的一些抖动。 DCM可以产生更低的抖动? 以上来自于谷歌翻译 以下为原文 I need to produce a set of video pixel clocks - 27 MHz, 74.25, 148.5 MHz, 297 MHz and switch from Clk to Clk/1.001 for each Clk rate. In previous projects (Spartan 3 - limited to 148.5 MHz max Clk) I've used a single DCM to produce all the necessary Clk rates fed from two external clocks (74.25 MHz and 74.25/1.001 MHz). For a new project I'm using a Spartan 6 and would like to consider using a single external clock to get both Clk and Clk/1.001 rates, but that requires a long cascade of DCM's and PLLs. Specifically, 27 MHz external CLk -> DCM0 -> DCM1 -> PLL0 produces both 74.25 MHz and 74.25/1.001 MHz clocks. then 74.25 MHz and 74.25/1.001 MHz clocks -> PLL1 produces all required video clks. The Clock Wizard reports the individual jitter for each DCM/PLL as DCM0 - 213 ps, DCM1 - 221 ps, PLL0 - 182 ps, PLL1 - 158 ps Can anyone advise if I could expect the jitter at the end of this 2 DCM & 2 PLL chain to be usable for video? Would I expect the jitter to be the square root of the sum of the squares of the 4 components (390 ps)? Or do the PLL's at the end of the cascade clean up some of the jitter of the previous PLL & DCM's to produce lower jitter? |
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奥斯汀写道:
... 你能为两个时钟中的每个时钟级联使用一个DCM和一个PLL吗? 我可以使用DCM& PLL获得74.25 / 1.001 MHz时钟,然后从剩余的DCM获得74.25 MHz时钟。然后BUFGMUX以提供最终的PLL输入。 这将是最佳解决方案并消除DCM级联。 (我实际上是从原来的级联架构中拿出另一个时钟,但我现在会用另一种方式。) 谢谢你的帮助。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 austin wrote:...I can use a DCM & PLL to get the 74.25 / 1.001 MHz clock, and then get the 74.25 MHz clock from the remaining DCM. Then BUFGMUX them to feed the final PLL input. That will be best solution and eliminate the DCM cascade. (I was actually picking up yet another clock from the original cascaded architecture, but I'll get that another way now.) Thanks for your help. View solution in original post |
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G,
通常,PLL会消除DCM的所有抖动。 问题是不支持DFS模式下的DCM,然后是DFS模式下的另一个DCM(不支持两个串联的合成器)。 具有DFS的DCM可以跟随DCM,其是相移(允许)。 也就是说,它可能会工作,但我们无法保证所有芯片都可以使用所有可能的级联M和D值。 Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 g, Generally, the PLL's remove all the jitter from the DCM's. The issue is that a DCM in DFS mode followed by another DCM in DFS mode is not supported (two synthesizers in series not supported). A DCM with DFS may follow a DCM which is phase shifting (allowed). That said, it will probaby work, but we cannot guarantee all silicon to work with all possible cascade M and D values. Austin Lesea Principal Engineer Xilinx San Jose |
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奥斯汀写道:
...问题是不支持DFS模式下的DCM以及DFS模式下的另一个DCM(不支持两个串联的合成器)...也就是说,它可能会工作,但我们无法保证所有芯片都可以使用 所有可能的级联M和D值。 谢谢,这是非常重要的信息。 我没有收到来自ISE 14.4的警告信息。 我的第一个DCM_CLKGEN是M = 11,D = 1,也是Clkout_Divide = 4 2ndoutput。 第二个DCM是M = 50,D = 77。 你能告诉我有关保证使用XC6SLX9 -3速度等级的任何信息吗? 否则,我可以去DCM0 - > PLL0 - > DCM1 - > PLL1。 我原以为使用串联的两个PLL对于抖动会更好。 也许这没关系。 以上来自于谷歌翻译 以下为原文 austin wrote:... The issue is that a DCM in DFS mode followed by another DCM in DFS mode is not supported (two synthesizers in series not supported)...That said, it will probaby work, but we cannot guarantee all silicon to work with all possible cascade M and D values. Thanks, that is very important info. I'm not getting a warning message about this from ISE 14.4. My first DCM_CLKGEN is a M=11, D=1, also a Clkout_Divide = 4 2nd output. The second DCM is a M=50, D=77. Can you tell me anything about that being guaranteed to work with XC6SLX9 -3 speed grade? Otherwise, I could go DCM0 -> PLL0 -> DCM1 -> PLL1. I had thought that using the two PLL in series would be better for jitter. Perhaps that doesn't matter. |
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G,
如果我记得,我检查过的M和D限制在1到31之间。 正如我所说,它可能有效,但没有任何保证。 在中间使用PLL可以消除抖动(几乎完全)。 你能为两个时钟中的每个时钟级联使用一个DCM和一个PLL吗? Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 g, If I recall, M and D are limited to 1 to 31 last I checked. As I said, it may work, but there are no guarantees. Using a PLL inbetween removes the jitter (almost completely). Could you use one DCM and one PLL in cascade for each of the two clocks? Austin Lesea Principal Engineer Xilinx San Jose |
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奥斯汀写道:
... 你能为两个时钟中的每个时钟级联使用一个DCM和一个PLL吗? 我可以使用DCM& PLL获得74.25 / 1.001 MHz时钟,然后从剩余的DCM获得74.25 MHz时钟。然后BUFGMUX以提供最终的PLL输入。 这将是最佳解决方案并消除DCM级联。 (我实际上是从原来的级联架构中拿出另一个时钟,但我现在会用另一种方式。) 谢谢你的帮助。 以上来自于谷歌翻译 以下为原文 austin wrote:...I can use a DCM & PLL to get the 74.25 / 1.001 MHz clock, and then get the 74.25 MHz clock from the remaining DCM. Then BUFGMUX them to feed the final PLL input. That will be best solution and eliminate the DCM cascade. (I was actually picking up yet another clock from the original cascaded architecture, but I'll get that another way now.) Thanks for your help. |
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