请问Spartan 6 DCM用户指南UG382.PDF版本1.7图3-15 DCM的驱动PLL有错误吗？

我注意到图3-15已经过各种编辑。
我认为DCM CLKIN（波形2）和CLKFBIN（波形3）的两个输入应该始终同意，前提是反馈环路闭合，DCM相位控制被锁定。
因此，我认为该图中的波形3必须是DCM的CLK0处的信号，而不是DCM的CLKFB处的信号，如图3-15中所示。
我认为CLKFBIN的信号与waveform2相同。
当然假设通过BUFG的延迟与通过IBUFG的延迟相同。
如果我不了解DCM的工作原理，有人可以纠正我吗？
否则，XILINX可以将此添加到此文档的勘误表中吗？
谢谢



以下为原文

I notice Figure 3-15 has undergone various edits.

I think that the two inputs to the DCM CLKIN (waveform 2) and CLKFBIN (waveform 3) should ALWAYS agree in phase provided the feedback loop is closed that the DCM phase control is locked.
Therefore, I think that waveform 3 in this drawing must be the signal at CLK0 of the DCM and NOT the signal at CLKFB of the DCM as annotated in Figure 3-15. I think that the signal at CLKFBIN is the same as waveform 2. This is assuming of course that the delay through BUFG is the same as the delay through IBUFG.

Can someone please correct me if I am not understanding how the DCM works?  Otherwise, can XILINX please add this to the errata for this document?

Thanks