在Spartan6中使用PLL

S，
PLL具有非常宽的输入捕获范围，即使不是数百MHz，也可以是数十甚至数十。
输入抖动非常重要，因为它太高，PLL可能会失锁，请参见数据手册。
PLL的“极点”约为300 KHz，并且还具有约1 MHz的另一个可选极点。
这些是根据输入频率，M和D值自动选择的。
你为什么在乎？
PLL将消除高频抖动（相位噪声）但除了跟踪较慢的变化率（低频抖动）之外无法做任何事情。
极需要一个电容器，不能做得太大（太多=太贵）。
同样，PLL与商用扩频时钟源兼容，通过在窄范围内扫描频率来降低​​EMI / RFI，然后再返回（通常是30KHz左右的三角形FM）。
您希望PLL跟踪SS时钟（跟随它）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

s,
 
The PLL has a very wide input capture range, many many tens if not hundreds of MHz.  The input jitter is important as if it is too high, the PLL may lose lock,  See the data sheet.
 
The "pole" for the PLL is at about 300 KHz, and also has another selectable pole at about 1 MHz.  These are selected automatically based on the input frequency, M and D values.
 
Why do you care?  The PLL will remove high frequency jitter (phase noise) but can not do anything but track slower rates of change (low frequency jitter).  The pole requires a capacitor, which can not be made very large (too much are=too expensive).  As well, the PLL is compatible with commercial spread spectrum clock sources which reduce EMI/RFI by sweeping their frequency across a narrow range, and back again (usually triangular FM at 30 KHz or so).  You want the PLL to track the SS clock (follow it).
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose