如何选择一个门控时钟输出为我的组件？

嗨，PSOC4的一个局限性是，它不可能使用时钟信号来实现时钟以外的任何其他目的。我需要一个门控时钟输出为我的组件。我知道通常的方法是使用一个比需要快两倍的时钟，但我怀疑是否可以用另一种方式。我试图在Verilog中实现一个“任何边缘T-FF”，它在编译设计时被“接受”，但是它引发了一个关于组合循环的通知。我还没有测试，如果这真的有效，我首先想弄清楚哪一个是更好的方法。如果我必须使用两倍更快的时钟，它是如何在组件中实现的？目前，我有一个状态机对每一个时钟脉冲作出反应，但如果上述适用，我的组件必须只对每第二个时钟脉冲作出反应。问候，Ralf



     以下为原文
          Hi, one of the PSoC4 limitations is that it's not possible to use a clock signal for any other purpose than clocking a component. I need a gated clock output for my component. I know that the usual way would be to use a clock two times faster than needed, but I wonder if it's possible by another way. I tried to implement a "any-edge T-FF" in Verilog, which is "accepted" when compiling the design, but it throws a notice about a combinational loop. I haven't tested yet if this really works, I first want to figure out which is the better way. If I have to use a two times faster clock, how is it implemented in the component? Currently I've a state machine which reacts on every clock pulse, but if the above applies, my component must only react on every 2nd clock pulse. Regards, Ralf