FPGA的时钟门控是好还是坏？

在ASIC中，将时钟分配给所有时钟元件的时钟树（一组网络和缓冲器）专门为每个器件构建。
结果，可以在树中具有几乎任何逻辑的时钟树来门控特定时钟或时钟组。
时钟树用于处理所有这些，包括通过门控元件来适应延迟。
在FPGA中，时钟树是固定的 - 它们是专用网络和缓冲区，负责将时钟分配给所有元素。
不可能在ASIC中进行任意可能的选通。
话虽这么说，FPGA时钟树有一些可以门控的元素。
时钟树的“根”是全局缓冲区。
它具有从最简单的“BUFG”到最复杂的“BUFGCTRL”（在某些架构中）的多种个性。
在所有架构中，它都具有BUFGCE的个性。
这是一个带时钟使能的全局时钟缓冲器。
如果使用得当（以及取决于你使用哪种设备和BUFGCE的味道），BUFGCE可以无故障地进行时钟门控。
但是，在大多数FPGA中，只有32个全局时钟网络 - 如果您想拥有多个门控时钟，则每个时钟使用这32个资源中的一个。
此外，在后来的架构（Virtex 6和7系列）中，时钟树上还有BUFH单元。
这些缓冲区是32个全局时钟网络的垂直脊线和进入每个时钟区域的水平时钟网络之间的连接点。
像BUFG一样，这些也有另一个人，BUFHCE。
同样，如果同步驱动这些单元的CE，则这些单元可以对进入时钟区域的时钟进行选通。
每个时钟区域有12个，因此设备中有更多。
限制是这些门控时钟中的每一个只能驱动一个时钟区域 - 因此使用这个门控时钟的所有逻辑必须适合一个时钟区域。
同样，如果使用正确，这些资源可确保无故障时钟门控。
此外，如果你只使用这些资源，那么从同一个源开始的所有时钟都会同步到达它们的目的地 - 只要它们都经过一个BUFG / BUFGCE / BUFGMUX / BUFGCTRL和零个或一个BUFH /
BUFHCE。
这些方法可用于降低系统功耗（通过关闭设计中不必要的部分），或者也可用于生成抽取时钟。
然而，使用任何其他资源进行选通是一个不同的故事。
如果您尝试使用LUT对时钟（例如）进行门控，则时钟需要离开时钟网络，使用通用路由资源路由到LUT，然后路由回可以到达所需时钟的时钟（可能是另一个）
BUFG或BUFH）。
很难确保LUT中的时钟门控是无干扰的，并且（更重要的是）所有额外的路由（包括额外的BUFG / BUFH）将使该时钟比停留在时钟树上的任何时钟晚到。
额外延迟的量可以从位置和路径运行到位置和路径运行而变化，并且还取决于过程，电压和温度。
FPGA中不建议使用这种门控。
最后一点（由另一张海报制作）是FPGA内的每个触发器都有一个CE引脚。
这可以防止更新FF的数据。
在某些情况下，您可以在不需要它们的值时关闭某些FF的更新 - 这可以通过工具自动完成，称为智能时钟门控。
通过减少FF不必要地改变状态的次数（以及因此由该FF驱动的所有逻辑），也可以降低系统的总功率。
我希望这有帮助。
Avrum



以下为原文

In ASICs, the clock tree (the set of nets and buffers) that distribute the clock to all clocked elements is built specifically for each device. As a result, it is possible to have clock trees with pretty much any logic in the tree to gate specific clocks or groups of clocks. The clock tree is built to handle all of this, including accomodating the delays through the gating elements.
 
In FPGAs, the clock trees are fixed - they are dedicated nets and buffers responsible for distributing the clock to all elements. It is not possible to do the arbitrary gating that is possible in ASICs.
 
That being said, the FPGA clock tree has certain elements that can be gated. The "root" of the clock tree is the global buffer. It has mutliple personalities from the simplest "BUFG" to the most complicated "BUFGCTRL" (in some architectures). In all architectures, it can have the personality of a BUFGCE. This is a global clock buffer with a clock enable. When used properly (and how depends on which device and which flavor of BUFGCE you use), the BUFGCE can do clock gating glitchlessly. However, in most FPGAs there are only 32 global clock networks - if you want to have multiple gated clocks, each clock uses one of these 32 resources.
 
In addition, in later architectures (Virtex 6 and the 7 series), there are also BUFH cells on the clock tree. These buffers are the connection points between the vertical spines of the 32 global clock nets and the horizontal clock nets that enter each clock region. Like BUFGs, these also have another personality, the BUFHCE. Again, if the CE of these cells is driven synchronously, these cells can gate the clock entering the clock region. There are 12 of these per clock region, so there are many more of them in a device. The restriction is each of these gated clocks can only drive one clock region - hence all logic that uses this gated clock must fit in one clock region.
 
Again, if used correctly, these resources guarantee glitchless clock gating. In addition, if you use ONLY these resources, then all the clocks that start at the same source all arrive at their destinations synchronously - as long as they all go through exactly one BUFG/BUFGCE/BUFGMUX/BUFGCTRL and either zero or one BUFH/BUFHCE. These approaches can be used to reduce system power (by shutting off unnecessary parts of your design), or can also be used for generating decimated clocks.
 
Gating using any other resource, however, is a different story. If you try and gate a clock (say) using a LUT, then the clock needs to leave the clock network, be routed using general routing resources to a LUT, and then be routed back to something that can reach the desired clocks (probably another BUFG or BUFH). It is very difficult to ensure that the clock gated in a LUT is glitch free, and (more importantly) all the extra routing (including the extra BUFG/BUFH) will make this clock arrive later than any clock that stays on the clock tree. The amount of extra delay is variable from place&route run to place&route run, and is also process, voltage and temperature dependent. This kind of gating is NOT recommended in FPGAs.
 
The last point (which was made by another poster) is that each flip-flop within the FPGA has a CE pin. This prevents the updating of the data of the FF. In some cases, you can turn off the updating of some FFs when their value is not needed - this can be done automatically by the tools, and is called intelligent clock gating. By reducing the number of times a FF changes state unecessarily (and hence all the logic driven by that FF), the overall power of the system can also be reduced.
 
I hope this helps.
 
Avrum

嗨
请查看此AR http://www.xilinx.com/support/answers/38099.htm进行时钟收集。



以下为原文

hi
 
Have a  look at this AR http://www.xilinx.com/support/answers/38099.htm for clock gatting.
 

感谢您的详细解释......这就是我所寻找的！
并感谢大家发送链接等等。谢谢！
:)



以下为原文

thanks for the detailed explanation ... this is what I was looking for! and thank you all for sending links etc .. thanks! :)