[问答]

如何在不使用BUFG的情况下从全局时钟引脚转换到FPGA逻辑？

问答对人有帮助，内容完整，我也想知道答案 0 嗨，我们有一个设计，我们正试图路由它。我们有8x 27MHZ时钟进入专用CLK引脚。在我们的VHDL内部，我们实例化IBUFG，将IBUFG的输出传递给FDCE而不是门，将其除以2（13.5MHZ）然后传递到BUFG。 BUFG的输出驱动逻辑。如果没有BUFG，即使在13.5MHZ CLK上也无法满足时序要求。我们的问题是LX150设备只有16个BUFG。我们仅将8x用于此模块，我们的整个系统需要20个。任何人都可以建议如何在不使用BUFG的情况下从全局时钟引脚转换到FPGA逻辑？我已经咨询过UG382第30页的一些想法，但仍然无法弄清楚如何避免BUFG。谢谢拉克兰。 Lachlan GroganCEO，SIL3 Pty LtdMelbourne，Australiahttp：//sil3.com.au 以上来自于谷歌翻译以下为原文 Hi, We have a design, we are trying to route it. We have 8x 27MHZ clocks comming into dedicated CLK pins. Internally in our VHDL we instantiate a IBUFG, pass the output of the IBUFG to a FDCE and NOT gate to divide it by 2 (13.5MHZ) and then pass into a BUFG. The output of the BUFG drives the logic. Wihtout the BUFG we can't meet timing, even on the 13.5MHZ CLK. Our problem is that the LX150 device only has 16 BUFG's. We use 8x of them for this module only, our entire system needs 20. Can anyone suggest how to go from Global Clock Pin to FPGA logic without the use of a BUFG? I have consulted UG382 page 30 for some ideas, but still can't work out how to avoid the BUFG. Thanks Lachlan. Lachlan Grogan CEO, SIL3 Pty Ltd Melbourne, Australia http://sil3.com.au 0
2019-7-1 10:20:35　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答举报钱杨静相关推荐 • FPGA中的全局时钟怎么用啊 2141 • 请问GCLK引脚是否连接到IBUFG？ 1630 • 在不使用ODDR的情况下转发时钟有什么意义吗？ 1197 • 全局时钟资源的例化方法有哪些？ 2130 • 从FPGA或PLD转换到门阵会遇到哪些时序问题？ 797 • 使用pll的时钟输出的正确方法是什么？ 3650 • Virtex 6，MMCM频率合成是什么 1506 • 为什么BUFG驱动DSP48E1的CE会出现问题？ 1337 • 请问从DCM环回中删除BUFG的优点/缺点是什么？ 1658 • 请问FPGAXCKU085FLVA1517-2-e的哪个引脚连接到系统时钟？ 2608 2个回答

答案对人有帮助，有参考价值 0 通常，非BUFG时钟的问题在于由于大的偏斜而导致保持时间失败一般路由。当我有比全局更多的输入时钟域时，我通常会做什么资源，是使用分布式内存来制作一个非常简单的同步器信号进入公共时钟域，通常比输入时钟略快。所有输入端的逻辑运行在非BUFG时钟上，使用备用边沿时钟。因此，在该非BUFG时钟的上升沿上改变的任何信号仅在该时钟上采样下降边缘，反之亦然。防止在本地时钟I上自动放置BUFG 添加BUFFER_TYPE属性“none”以及USELOWSKEWLINES。这习惯了在Spartan 2这样只有4个全局时钟的旧版FPGA上更频繁地出现缓冲区。这是一个来自这个方法的计数器的verilog示例，我用它作为写分布式RAM的地址。请注意，它需要两倍的寄存器来处理交替的时钟边缘： //写地址计数器是两个阶段，以避免时钟偏差问题@（posedge in_clk或posedge clr）开始if（clr）wa else wa //注意来自相反时钟寄存器的反馈，而不是“wa + 1”endalways @（negedge in_clk或 posedge clr）如果（clr）wb else wb结束则开始 - Gabor - Gabor 在原帖中查看解决方案以上来自于谷歌翻译以下为原文 Usually the problem with non-BUFG clocks is that you fail hold time due to the large skew in the general routing. What I typically do when I have more input clock domains than global resources, is to make a very simple syncronizer using distributed memory to bring the signals into a common clock domain, usually slightly faster than the input clocks. All of the logic on the input side, which runs on the non-BUFG clock, uses alternate edge clocking. So any signal that changes on a rising edge of this non-BUFG clock is only sampled on the falling edge, and vice versa. To prevent automatic BUFG placement on the local clocks I add a BUFFER_TYPE attribute of "none" and also USELOWSKEWLINES. This used to crop up more frequently on much older FPGA's like Spartan 2, which had only 4 global clock buffers. Here's a verilog example of a counter from this method, which I used as the write address of the distributed RAM. Note that it requires twice the registers to deal with the alternating clock edges: // Write address counter is two stage to avoid clock skew problems always @ (posedge in_clk or posedge clr) begin if (clr) wa <= 0; else wa <= wb + 1; // Note feedback from opposite clocked register, not "wa + 1" end always @ (negedge in_clk or posedge clr) begin if (clr) wb <= 0; else wb <= wa; end -- Gabor -- GaborView solution in original post

2019-7-1 10:36:03 评论举报杨玲

答案对人有帮助，有参考价值 0 通常，非BUFG时钟的问题在于由于大的偏斜而导致保持时间失败一般路由。当我有比全局更多的输入时钟域时，我通常会做什么资源，是使用分布式内存来制作一个非常简单的同步器信号进入公共时钟域，通常比输入时钟略快。所有输入端的逻辑运行在非BUFG时钟上，使用备用边沿时钟。因此，在该非BUFG时钟的上升沿上改变的任何信号仅在该时钟上采样下降边缘，反之亦然。防止在本地时钟I上自动放置BUFG 添加BUFFER_TYPE属性“none”以及USELOWSKEWLINES。这习惯了在Spartan 2这样只有4个全局时钟的旧版FPGA上更频繁地出现缓冲区。这是一个来自这个方法的计数器的verilog示例，我用它作为写分布式RAM的地址。请注意，它需要两倍的寄存器来处理交替的时钟边缘： //写地址计数器是两个阶段，以避免时钟偏差问题@（posedge in_clk或posedge clr）开始if（clr）wa else wa //注意来自相反时钟寄存器的反馈，而不是“wa + 1”endalways @（negedge in_clk或 posedge clr）如果（clr）wb else wb结束则开始 - Gabor - Gabor 以上来自于谷歌翻译以下为原文 Usually the problem with non-BUFG clocks is that you fail hold time due to the large skew in the general routing. What I typically do when I have more input clock domains than global resources, is to make a very simple syncronizer using distributed memory to bring the signals into a common clock domain, usually slightly faster than the input clocks. All of the logic on the input side, which runs on the non-BUFG clock, uses alternate edge clocking. So any signal that changes on a rising edge of this non-BUFG clock is only sampled on the falling edge, and vice versa. To prevent automatic BUFG placement on the local clocks I add a BUFFER_TYPE attribute of "none" and also USELOWSKEWLINES. This used to crop up more frequently on much older FPGA's like Spartan 2, which had only 4 global clock buffers. Here's a verilog example of a counter from this method, which I used as the write address of the distributed RAM. Note that it requires twice the registers to deal with the alternating clock edges: // Write address counter is two stage to avoid clock skew problems always @ (posedge in_clk or posedge clr) begin if (clr) wa <= 0; else wa <= wb + 1; // Note feedback from opposite clocked register, not "wa + 1" end always @ (negedge in_clk or posedge clr) begin if (clr) wb <= 0; else wb <= wa; end -- Gabor -- Gabor

2019-7-1 10:50:46 评论举报杨玲