为什么DCM会限制输出频率？

DCM是一种复杂的外来资源，它使设计人员能够以比FPGA的标准IOB和CLB的基本速度快几十或几百倍的粒度处理信号。
设计人员应该使用DCM来创建高精度的高速参考时钟。
对于您提到的类型的低速时钟，您应该从DCM开始创建最高速时钟，然后使用传统的数字分频器来获得您的低速时钟。
你提到的最快时钟小于13Mhz。
你根本不需要DCM。
但是，您可能正在实施ITU TDM方案，因此您可能在设计中的某处有一个外部参考时钟。
您可能会使用此参考时钟来调节内部最高速时钟，您可能会使用DCM。
从那里使用标准分隔线。



以下为原文

A DCM is a complex, exotic resource that lets the designer work with signals at a granularity that is tens or hundreds of times faster than the basic speed of the standard IOBs and CLBs of the FPGA. The designer is supposed to use the DCM to create highly precise high-speed reference clocks.  For lower-speed clocks of the type you mention, you  should start with a DCM to create your highest-speed clock, and then use traditional digital dividers to derive your lower-speed clocks. The fastest clock that you mention is  less than 13Mhz. You don't really need a DCM at all. However, it seems likely that you are implementing a ITU TDM scheme, so you probably have an external reference clock somewhere in your design. You will likely use this reference clock to condition your internal highest-speed clock, for which you will probably use a DCM. Use standard dividers from there.