[问答]

如何使XC3S200 FPGA以理想的占空比输出时钟？

问答对人有帮助，内容完整，我也想知道答案 0 亲爱的，我的朋友，我发现XC3S200 FPGA会降低时钟占空比。当我将占空比为50.3％的时钟输入FPGA时，如果我进行如下连接，则占空比变为约53％：时钟输入引脚 - > BUFG - >时钟输出引脚。如果我进行这样的连接，则占空比变为大约56％：时钟输入引脚 - > DCM - >输出引脚。为什么DCM的职责修正功能不起作用？如何使XC3S200 FPGA以理想的占空比输出时钟？非常感谢！我期待着您的回复。以上来自于谷歌翻译以下为原文 dear my friend, I find that the XC3S200 FPGA deteriorated the clock duty.When I input the clock with the duty of 50.3% into FPGA, however, the duty turns to about 53% if I make connections like this: clock input pin-> BUFG ->clock output pin. Anymore, the duty turns to about 56% if I make connections like this: clock input pin -> DCM -> output pin. Why doesn't the function of duty correction of DCM work? How can I make the XC3S200 FPGA output the clock with ideal duty? Thanks a lot! I will look forward to hearing from you. 0
2019-5-9 12:44:41　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答举报陈福蓓相关推荐 • XC3S200配置出现问题 2309 • 怎么在Xilinx Spartan-3 XC3S200 FPGA中使用鼠标 2476 • 请问s3不支持AXI怎么办？ 1246 • 设备未在影响时显示 1061 • 合成面积大于FPGA面积 1547 • CYCLONE IV 如何输出一个大驱动的200MHz时钟波形？ 5197 • 请问有xc3s200-tq144配置图吗？ 1963 • 如何利用Verilog设计液晶显示控制器？ 1292 • buck电路实物占空比与理想占空比 4748 • 请问时钟输入上的Virtex 7 IDELAY会导致占空比失真吗？ 1410 1个回答

答案对人有帮助，有参考价值 0 首先，您没有提及您的时钟频率，但随着频率上升，DCM将占空比调整为50％的能力变得不那么准确。这是由于用于生成DCM的输出波形的固定延迟元件。 DCM不是Spartan 3中的锁相环。无论如何，我发现FPGA不太可能比你在Spartan 3中的50.3％占空比做得更好。在较高频率下，占空比测量受信号阈值电平的影响很大，因为信号花费的时钟周期的较大部分从低电平变为高电平或从高电平变为低电平。将时钟驱动到输出引脚也可以改变占空比由于低到高与高到低传播延迟的差异。您可以通过使用差分IO标准（如LVDS）来最小化此类问题。通过在内部全局时钟信号的两个边沿上使用的DDR IOB输出寄存器，可以最佳地再现输出引脚的内部时钟信号。该方法用于所有DDR存储器设计，用于驱动外部SDRAM芯片的时钟。关于时钟信号完整性有很多应用笔记，包括占空比和周期到周期抖动。这些都表明FPGA不是用作时钟源的理想元件。 DCM不会减少周期抖动，正如我所提到的，它们调整占空比的能力受到延迟链的离散性质的限制。您还没有说过为什么50.3％的占空比在您的应用中不够好，但我建议您为生成时钟而不是使用FPGA寻找专用的PLL芯片解决方案。问候，的Gabor - Gabor 以上来自于谷歌翻译以下为原文 First of all, you don't mention your clock frequency, but as the frequency goes up the ability of the DCM to adjust the duty cycle to 50% becomes less accurate. This is due to the fixed delay elements used to generate the output waveform of the DCM. The DCM is not a phase-locked loop in Spartan 3. In any case I find it unlikely that an FPGA can do better than the 50.3% duty cycle that you are putting into the Spartan 3. At higher frequencies, the duty cycle measurement is affected greatly by the threshold level of the signal, since the signal is spending a larger portion of the clock cycle transitioning from low to high or high to low. Also driving a clock to an output pin can change the duty cycle justdue to differences in the low-to-high vs high-to-low propagation delays. You can minimize this sort of problem by using a differential IO standard like LVDS. Your best reproduction of an internal clock signal to an output pin will come by using the DDR IOB output register clocked on both edges of the internal global clock signal. This method is used in all of the DDR memory designs for driving the clocks to the external SDRAM chips. There are a lot of application notes about clock signal integrity including duty cycle and cycle to cycle jitter. These all point to the fact that an FPGA is not an ideal component to use as a clock source. DCM's will not reduce cycle jitter, and as I mentioned, their ability to adjust the duty cycle is limited by the discrete nature of their delay chains. You haven't said why 50.3% duty cycle is not good enough in your application, but I would suggest looking for a dedicated PLL chip solution for your clock generation rather than using an FPGA. Regards, Gabor -- Gabor

2019-5-9 12:52:20 评论举报杨玲