XC3S200配置出现问题

嗨，
我用基于ARM的微控制器和XC3S200创建了一块电路板。
FPGA在Slave Parallel模式下编程，配置过程（使用.bit文件）似乎没问题：在INIT_B上没有发出错误信号，DONE在整个.bit文件（用ISE 8.2i创建）发送之前高达5个字节
到FPGA，FPGA输出引脚停止驱动为高电平。
问题是输入时钟信号（频率40 MHz）可以通过简单的逻辑门（仅用于测试）从时钟输入（GCLK引脚之一）传递到任何输出引脚（我可以在示波器上观察到），
但不驱动任何连接（时钟输入）触发器。
所有触发器看起来都像是永久复位（清除）。
我有一个带有JTAG编程的XC3S200的测试板，它在几乎相同的配置中没有出现这样的问题。
主要区别在于外部时钟连接到普通I / O引脚之一，而不是GLCK引脚。
这可能是配置编程的问题吗？
我应该做什么不同于JTAG编程，让Slave Parallel配置文件好吗？
或者因为使用GLCK引脚作为外部时钟输入而出现问题？
在此先感谢您的任何建议。
马尔钦



以下为原文

Hi,

I have created a board with an ARM-based microcontroller and XC3S200. FPGA is programmed in Slave Parallel mode, and the configuration process (using .bit file) seems to go fine: no error is signalled on INIT_B, DONE goes high 5 bytes before the entire .bit file (created with ISE 8.2i) is sent to the FPGA, and the FPGA output pins stop driving high.

The problem is that the input clock signal (frequency 40 MHz) can be passed from a clock input (one of GCLK pins) to any output pin (I can observe this on an oscilloscope) via simple logical gates (made for tests only), but does not drive any connected (clock input) flip-flops. All flip-flops look like permanently reset (cleared). I have a test board with XC3S200 programmed by JTAG which did not exhibit such a problem in a virtually identical configuration; the main difference is that the external clock was connected to one of ordinary I/O pins, not to GLCK one.

Can it be a problem with configuration programming? What should I do differently than for JTAG programming, to get Slave Parallel configuration file ok? Or there is a problem because of using a GLCK pin as the external clock input?

Thanks in advance for any suggestions.

Marcin