xilinx 14.1 Xpower分析器警告时钟都没有约束

1.如果您检查综合报告（甚至是设计摘要中的时钟报告）是否有任何时钟未由您定义但是由综合推断（Synplify，XST，等等）？
如果是这样，那就是questionableHDL的结果。
2.对于任何用途的功率分析仪，您需要为分析仪的输入提供一些切换速率。
当然，没有输入切换，就不会有太多活动。
此外，所讨论的模块可能是如此低的功率，它不会在x小数位范围内注册，因此向下舍入为0。
没有看到任何一个问题的报告，它只是猜测工作......
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

1. If you check the synthesis report (or even the Clock report from the Design summary) are there any clocks that are not defined by you but are inferred by synthesis (Synplify, XST, whatever)? If so, that's the result of questionable HDL.
 
2. For the power analyser to be of any use, you need to provide some toggle rates for your inputs into the analyser. Naturally, with no input toggling, there won't be much activity. Also, the module in question might be so low power that it doesn't register in the x decimal places range and so is rounded down to 0.
 
Without seeing the reports for either question, it's just guess work ... 
----------
"That which we must learn to do, we learn by doing." - Aristotle

嗨hgleamon1，
感谢您的回复。
1）在xilinx设计摘要（后PAR）中，仅显示了我定义的时钟。
所有限制都得到满足。
没有推断出额外的时钟 - 成功实施。
当我在设计中使用PLL o / p时钟时，我只在Xpower Analyzer中获得“所有时钟未定义”警告。
如果我移除PLL并在顶层模块中声明所有PLL o / p时钟（作为i / p）并在UCF中约束它们，则此警告消失。但它仍然不会改变整体功耗或使用的子模块
0电源
2）对于这个，我不知道 - 为什么一些子模块显示0功率。
我非常肯定子模块没有被synopsys修剪掉（因为synplify和XST都显示了几乎相同的资源使用）。
和切换率设置为默认值（12.5％）。
我附上了电力报告。
我更关心一些显示0功率的子模块。
关于这个的任何指针？
附上的电源报告适用于我使用PLL时钟o / p的情况。
所以 - 所有时钟未定义警告仍然在报告中。
然而，即使我确实移除了PLL并限制了UCF中的所有时钟，警告也消失了，但功率没有太大变化，一些子模块仍然显示0（在层次功率部分）。
帮助:) ...提前谢谢。
ž。
lvds_test_top.pwr 205 KB



以下为原文

hi hgleamon1,
 
thanks for your reply.
 
1) in the xilinx design summaries (post PAR), only clocks which i defined are being shown. all constraints were met. no additional clocks were inferred - successful implementation.
 
i only get the "all clocks not defined" warning in Xpower Analyzer when i use a PLL o/p clocks in the design. if i remove the PLL and declare all the PLL o/p clocks in the top module (as i/p) and constraint them in the UCF, then this warning disappears. but it still doesnt change the overall power consumption or the submodules that use 0 power
 
2) for this one, i have no idea - why some of the submodules show 0 power. im quite certain the submodules are not getting trimmed away by synopsys (because synplify and XST, both show almost same resource usage). and toggle rates are set to default (12.5%). i've attached the power report. im more concerned about some submodules showing 0 power. any pointers on this?
 
the power report attached is for when i use PLL clock o/p. so the - all clocks not defined warning is still there in the report. however even when i did remove the PLL and constraint all the clocks in the UCF, the warning went away but the power didn't change much and some of the sub modules still showed 0 (in the heirarchial power section).
 
help :) ... thanks in advance. 
 
z.
            lvds_test_top.pwr ‏205 KB

您是否已阅读并理解所附报告的2.4置信水平部分中给出的注释和指导？
我得到的印象是，您需要进入功率分析仪并更加主动地使用信号（尽管我已经很长时间没有使用功率分析仪工具）。
- 编辑
另外，从第4节警告：
--------------------------------------------------
------------------------------警告：PowerEstimator：270  - 功耗估算被认为是不准确的。
要查看详细信息，请使用“-v”开关生成高级报告。警告：电源：1337  - 时钟网络的时钟频率“MMCM_PHASE_CALIBRATION_ML_LUT2_75_ML_NEW_CLK”为零。警告：电源：1337  - 时钟网络的时钟频率“pll74m74m148m / mmcm_adv_inst_ML_NEW_I1”为
零。
你应该试着找出为什么XPA认为这些时钟频率为零......
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

Have you read and understood the notes and guidance given in the section 2.4 Confidence Level of the attached report?
 
I get the impression that you need to go into the Power Analyser and be more proactive with the signalling (although I haven't used the power analyser tool for quite some time).
 
-- edit
 
Also, from section 4 Warnings:
 
--------------------------------------------------------------------------------
WARNING:PowerEstimator:270 - Power estimate is considered inaccurate. To see details, generate an advanced report with the "-v" switch.
WARNING:Power:1337 - Clock frequency for clock net "MMCM_PHASE_CALIBRATION_ML_LUT2_75_ML_NEW_CLK" is zero.
WARNING:Power:1337 - Clock frequency for clock net "pll74m74m148m/mmcm_adv_inst_ML_NEW_I1" is zero.
 
You should try to figure out why XPA thinks these clocks have zero frequency ...
 
----------
"That which we must learn to do, we learn by doing." - Aristotle

嗨hgleamon1，
是！
我已经阅读了2.4节的摘要并提出了从低到中的置信水平......
对于时钟 - 就像我说的，如果我将时钟指定为顶部模块的i / p并在ucf中约束它们而不使用pll o / p，那么时钟的置信度会上升到高（不确定为什么xpower不是
正确选择pll时钟）
对于io节点活动 - 我检查了摘要细节，甚至在为所有io指定一些活动率后，功率仍然没有增加太多（仅.002W左右）
我们还试图将信号活动率添加到其他模块/资源 - 这样可以改变功率......就像0.00001 W一样
ž。



以下为原文

hi hgleamon1,
 
yes! i had already read the 2.4 section summary and brought up the confidence level from low to medium ...
 
for the clocks - like i said, if i specify the clocks as i/p to top module and constraint them in ucf and not use pll o/p, then the confidence level of clock goes up to high (not sure why xpower is not picking the pll clocks properly)
 
for io node activity - i checked in the summary details and even after specifying some activity rate for all the io, the power still doesn't increase much (just .002W or so)
 
have also tried to add signal activity rates to other modules/resources - this gives v v litte change in power ... something like 0.00001 W
 
z.
 
 

你有没有改变这些警告？
xpa时我有同样的警告。
我很好奇如何认真改变这些警告。
警告如下： 
时钟网络的时钟频率“ale_i_BUPFG”为零。
但是ale_i_BUPFG不是时钟信号。
如果您已经解决了这些问题，请告诉我如何解决。
此致。



以下为原文

Have you ever changed these warnings? I had the same warnings when did xpa. And I am curious about how to change these warning seriously.
warning as followed:
  clock frequency for clock net "ale_i_BUPFG" is zero.
but ale_i_BUPFG is not a clock signal.
If you have fixed these problems,could you plese tell me how.
yours sincerely.