如何消除负面松弛？

嗨，
为什么你想把TIG放在那个负面的松弛路径上？
这是一条错误的道路吗？
请检查时间报告中的路径，看看为什么松弛是负面的。
首先分析负时间路径，然后看看如何克服这个问题。
有关更多详细信息，请参阅ug612，第8章。
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug612.pdf



以下为原文

Hi,
 
Why you want to put TIG on that negative slack path?
Is it a false path?
 
Please check the path in timing report and see why the slack is negative.
First analyze the negative timing path and then see how to overcome this.
Please refer to ug612,chapter 8 for more details.
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug612.pdf

嗨，
如果失败的路径是有效的数据路径，那么您不应该使用TIG。
TIG的路径将被视为对于在设备上放置更远的时间结果而言并不重要。
如果逻辑是有效的数据路径，则工具将以不正确的方式放置逻辑。
如果逻辑电平太多，工具无法对其进行优化以使其适合1个时钟周期，则需要分析路径。
您还需要考虑这是否是有效的多周期路径。
根据路径报告，您需要确定延迟是否受组件延迟或路由延迟的影响。
问候，
KR
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以下为原文

Hi,
 
If the failing path is valid data path, then you should not use TIG. TIG'ed path will be treated as no importance for meeting timing results in placing then farther on device. Tool will place the logic in the way which is not correct if it is valid data path.
 
You need analyse the path if you have too many logic level and tool can not optimize it to make it to fit for 1 clock cycle.
You also need to consider if this is a valid multicycle path.
 
Based on the path report you need to decide if the delay is affected by component delays or routing delays.
 
Regards,
KR
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嗨，
负松弛是指设计在给定频率下不起作用的通知。
您需要首先分析具有负松弛的路径。
该路径的来源和目的地是什么。
1）如果源和目标由相同的时钟触发，那么它是用于时序分析的有效数据路径，您不能忽略具有TIG约束的路径。
您需要找出该路径失败的原因，并且需要修复设计才能在硬件上工作。
2）如果失败路径在两个不同的时钟域之间。
（即，clk1触发源，clk2触发目标）然后检查两个时钟之间是否存在任何关系。
如果clk1和clk2都相关，则使用其他约束，如多循环路径。
如果您有疑问，可以发布您的时间报告* .twr文件，我会检查并相应地为您提供建议。
注意：TIG会忽略时间分析并给你通过结果，但实际上你只是隐瞒真相。
当您将设计转储到硬件时，如果失败路径是用于分析的有效数据路径，则它将完全失败。
谢谢，
佳日



以下为原文

Hi,
 
Negative slack is notification that the design will not work on given frequency.
You need to first analyze the path with negative slack.
 
What is the source and destination of that path.
1) If source and destination is triggered by same clock then it's valid data path for timing analysis and you cannot ignore that path with TIG constraints.
You need to find out why that path is failing and need to fix for design to work at hardware.
 
2) If the failing path is between two differnt clock domain. (i.e. source is triggered by clk1 and destination by clk2) then check if there is any relation between two clocks or not. If both clk1 and clk2 are related then use other constraints like multi-cycle path.
 
If you have doubt you can post your timing report *.twr file I will check and provide you the suggestions accordingly.
 
NOTE: TIG will ignore the timing analysis and gives you passed result but actully you are just hiding the truth. When you dump your design at hardware it will definetly fail if failing path is valid data path for analysis.
 
Thanks,
Yash
 

嗨，
这不会破坏逻辑，但不会分析路径。
这是一个快速示例http://www.xilinx.com/support/answers/10025.html
--Hem
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以下为原文

Hi,
 
This will not damage the logic, but it will not analyze the path.
 
Here is a quick example http://www.xilinx.com/support/answers/10025.html
 
--Hem
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这不会破坏逻辑，但不会分析路径。
这一评论可能令人困惑，并有一些澄清。
正如其他人所评论的那样，如果你在路径上放置一个TIG，那么该工具将忽略路径上的时间。
虽然组合功能的功能仍然是“正确的”，但系统的功能几乎肯定是不正确的。
同步RTL设计背后的整个概念是所有路径都不需要比时钟关系所允许的更多的传播延迟 - 对于单个时钟系统，这意味着所有路径都需要不超过一个时钟周期的传播时间。
如果不是这样，则注册转移语言的概念就会被打破。
换句话说，同步RTL（对于一个时钟系统）是有效的，因为我们描述了寄存器之间的寄存器和传递函数。
我们所做的描述是周期精确的 - 它隐含地假设传输将给定周期的状态转换为下一周期的状态（基于输入）。
这要求组合路径小于一个时钟周期。
如果即使一条路径需要多于一个时钟周期，那么来自一个状态的传递函数将最终影响当前状态之后的第二个时钟上的状态。
这是不正确的;
设计（实施后）将不再适用于您的周期精确RTL描述。
这是静态时序分析和约束的全部原因 - 因此实现工具可以检查这种使RTL设计成为可能的基础和隐式假设。
Avrum



以下为原文

This will not damage the logic, but it will not analyze the path.
 
This comment could be confusing and bears some clarification.
 
As others have commented, if you put a TIG on the path, then the tool will simply ignore the timing on the path. While the functionality of the combinatorial function will still be "correct", the functionality of your system will almost certainly be incorrect.
 
The whole concept behind synchronous RTL designs is that all paths require no more propogation delay than is allowed by the clock relationships - for a single clock system, this means that all paths require no more than one clock period of propagation time. If this is not true then the concept of Register Transfer Language is broken.
 
Stated another way, synchronous RTL (for a one clock system) works because we decribe the Registers and the Transfer functions between the registers. The description we make is cycle accurate - it implicitly assumes that the transfers transform the state at a given cycle to the state at the next cycle (based on the inputs). This requires that the combinatorial paths be less than one clock period. If even one path takes more than one clock period, then the transfer function from one state will end up affecting the state on the SECOND clock after the current state. This is incorrect; the design (after implementation) will no longer function correctly with respect to your cycle accurate RTL description.
 
This is the whole reason for static timing analysis and constraints - so that the implementation tools can check this underlying and implicit assumption that makes RTL design possible.
 
Avrum

HI，
如何消除负面松弛？
答：是设置松弛还是保持松弛。
基于此，您可以根据所考虑的路径采用不同的方法。
有时降低时钟频率应该摆脱负面松弛。
如果我把时间忽略constriant放到松弛路径上，它会破坏逻辑吗？
答：这取决于您分析的路径。
如果找到负斜率的路径不需要时序约束，那么可以对其设置TIG约束。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

HI,
 
How to remove negative slack?.
A: Is it Setup slack or Hold slack. Based on this you have different approaches based on the path under consideration. Sometimes decreasing the clock frequency should get rid of the negative slack.
 
If i put timing ignore constriant to slack path, will it damage the logic?
A: It depends on the path which you are analyzing. If the path which you find negative slack does not need a timing constraint then you can put a TIG constraint on it.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

嗨，我希望你得到你的答案，如果是的话请用标记接受的解决方案关闭线程。谢谢，Yash



以下为原文

Hi,

I hope you got your answer, if yes please close the thread with marking accepted solution.

Thanks,
Yash