从ome master virtex fpga到9 slave fpgas的时钟分配怎么实现

你有没有提到主设备和从设备之间的定时“同步”（或耦合）需要什么？
这是对您第一篇文章的引用。
除了可靠的数据传输之外，主站和从站之间是否还有其他（未说明的）时序要求？
鉴于时钟将在每个从器件上使用DCM或PLL进行再生，是否有任何有用的目的可以分配比100MHz（或50MHz）更快的时钟？
我打算使用相同的时钟在主设备和从设备之间进行数据传输，以及生成400Mhz时钟。
rcingham可能有一个有趣而又不同于我的方法，而rcingham完全正确地提醒我们所有人（特别是我）有一个以上可能和理性的解决方案。
换句话说 - 使用常用的美国口语 - 有一种方法可以给猫皮肤。
这是一种看似可行的方法：
主：
生成200MHz时钟，用于参考和全局逻辑系统分配，并在器件内使用。
用于以每通道400Mbit / sec速率传输和接收串行数据（使用DDR时钟模式）。
生成9个50MHz时钟的相同副本，以便分发给9个从站。
如果简单的数据传输是唯一的时序和同步要求，那么单端（而不是差分）传输就足够了。
此时钟的使用很简单且有限：为主设备和所有从设备提供公共时基。
从站：
从50MHz时基时钟（从Master接收）重新生成（使用PLL）200MHz时钟，用于参考和全局逻辑系统分配并在器件内使用。
用于串行数据的发送和接收（DDR模式）。
两个主人和奴隶：
所有这些都使用源自Master的时基参考生成的通用200MHz时基。
所有这些都以每通道400Mbits / sec的速度接收串行数据，与200MHz（本地复制）全局时钟具有不确定的相位对齐。
所有输入串行数据通道都需要使用可变延迟模式的IODELAY模块与本地200MHz时钟对齐，这需要使用IDELAYCTRL模块。
主设备和从设备之间的所有串行输入和输出数据互连将是差分对（例如LVDS_25）。
使用200MHz（DDR或半比特率）时钟和IDDR和ODDR模块，不需要使用ISERDES和OSERDES模块。
该结构可处理200MHz全局结构时钟和与IDDR和ODDR模块的内部半速率数据连接。
如果需要较低频率的全局系统时钟，则可能优选使用ISERDES和OSERDES块。
使用IODELAY块将输入串行数据与本地200MHz时钟对齐的优点是：
互连长度匹配不再是一个问题
主设备和从设备之间的热梯度不再是一个问题
每个从设备可以重新生成自己的本地串行速率时钟，从主设备锁定到时基
从主站到从站的时基分布可以是低频（低EMI），低成本（单端，单引脚）
这有意义吗？
请记住，我将100％的设计时间花在Spartan-6上，而不是Virtex（5或6），所以我可能会做出一些愚蠢和错误的假设。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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在原帖中查看解决方案



以下为原文

Did you ever mention what you require for timing 'synchronisation' (or coupling) between the master and slaves?
 
This is a reference to your first post.  Other than reliable data transfer, is there any other (unstated) timing requirement between the master and the slaves?
 
Given that the clock will be regenerated with a DCM or PLL at each slave, is there any useful purpose for distributing a clock faster than 100MHz (or 50MHz, for that matter)?
 
i intend to use the same clock for data transfer  between master and slaves as well as for generating 400Mhz clock.

 
rcingham may have an interesting and yet different approach than mine, and rcingham is entirely correct in reminding all of us (particularly me) that there is more than one possible and rational solution.  In other words -- to use a commonly used American colloquialism -- there is more than one way to skin a cat.  Here is an approach which seems workable:
 
MASTER:
 

• Generates 200MHz clock for reference and global logic system distribution and use within the device.  Used for transmission and reception of serial data at 400Mbit/sec rate per channel (using DDR clocking mode).
  

• Generates 9 identical copies of 50MHz clock for distribution to the 9 slaves.  If simple data transfer is the only timing and synchronisation requirement, then single-ended (rather than differential) transmission is entirely adequate.  The usage of this clock is simple and limited:  provide a common timebase for the master and all slaves.
  

 
SLAVES:
 

• Re-generates (using PLL) from 50MHz timebase clock (received from Master) a 200MHz clock for reference and global logic system distribution and use within the device.  Used for transmission and reception of serial data (DDR mode).
  

 
BOTH MASTER AND SLAVES:
 

• All are using a common 200MHz timebase generated from timebase reference sourced from the Master.
  

• All are receiving serial data at 400Mbits/sec per channel, with indeterminate phase alignment to the 200MHz (local copy) global clock.
  

• All input serial data channels will need to be aligned to the local 200MHz clock using an IODELAY block in variable delay mode, which requires the use of IDELAYCTRL block.
  

• All serial input and output data interconnect between master and slaves will be differential pairs (e.g. LVDS_25).
  

• Using a 200MHz (DDR, or half-bitrate) clock and IDDR and ODDR blocks, the use of ISERDES and OSERDES blocks isn't required.  The fabric can handle a 200MHz global fabric clock and the internal half-rate data connections to the IDDR and ODDR blocks.  If a lower frequency global system clock is desired, then using the ISERDES and OSERDES blocks may be preferred.
  

 
The advantages of using the IODELAY blocks to align the incoming serial data to the local 200MHz clock are:
 

• interconnect length matching is no longer a concern
  
• thermal gradients between master and slaves is no longer a concern
  
• each slave can re-generate its own local serial rate clock, locked to timebase from the master
  
• timebase distribution from master to slaves can be low frequency (low-EMI), lower-cost (single ended, single pin)
  

 
Does this make sense?  Keep in mind, I spend 100% of my design time in Spartan-6 land, not Virtex (5 or 6), so I may have made some silly and mistaken assumptions.
 
-- Bob Elkind
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从卡如何连接到主卡？它们是否在同一个背板上？
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

How are the slave cards connected to the master card?
Are they on the same backplane?

------------------------------------------
"If it don't work in simulation, it won't work on the board."

是和否，
如果我们决定使用并行总线，那么YES。
否则我打算在主设备和从设备之间使用专用的9 LVDS（SERDES）链路。
但我不确定哪种方法最适合这两种方法。
或者还有其他方法。



以下为原文

Yes and No,
 
if we decide to use parallel bus then YES.
 
else i am planning to use dedicated 9 LVDS(SERDES) links between master and the slaves.
 
But i am not sure which approach will be best out of these two.
Or is there any other approach also. 

我想同步所有9个从属卡的操作。
具体来说，你有什么想法？
“同步操作”可以有许多合理的含义。
我还希望主卡和从卡之间的数据传输速率为300-400Mbps。
300-400Mbits / sec的单个串行通道（最好是差分）完全在Virtex-5器件的功能范围内。
你需要300-400 Mbits / sec的主机，还是只需要一个方向？
通常，master => slave要求比slave => master数据传输要温和得多。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

i want to synchronise the operation of all the 9 slave cards.
 
What do you have in mind, specifically?  "Synchronise the operation" can have a number of plausible meanings.
 
i also want to have data transmission between master and slave cards at 300-400Mbps rate.
 
A single serial channel (preferably differential) at 300-400Mbits/sec is well within the capabilities of Virtex-5 devices.  Do you need 300-400 Mbits/sec both to and from the master, or just in one direction?  Often the master => slave requirements are much more modest than slave => master data transfers.
 
-- Bob Elkind
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所有从属卡都连接到同一芯片（DUT）。
这些从设备由来自DCM的400Mhz时钟提供时钟。该时钟用于以400Mbps速率向DUT驱动数据。
要求是来自从属设备到此DUT的信号应对齐（此信号之间的偏差不超过100ps至200ps）。
来到第二点是的我需要从奴隶到师父的数据传输。



以下为原文

All the slave cards are interfaced to the same chip(a DUT). The slaves are clocked by a 400Mhz clock from DCM.This clock is used to drive data at 400Mbps rate to DUT.
The requirement is that the signals coming from the slaves to this DUT shall be aligned (skew between this signals no more than 100ps to 200ps). 
 
coming to second point yes i need data transfer from slaves to Master .

听起来你有一个可行的解决方案，只要从时钟来自DUT（主设备）。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Sounds like you have a workable solution, as long as the slave clocks originate from the DUT (master).
 
-- Bob Elkind
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建议：确保所有主从时钟分配距离名义上相同。确保所有从站到主站的数据分配距离名义上相同。这对于有线链路而不是背板链路更容易。
购买和使用一套现成的电缆组件，而不是让当地友好的线人组装，因为他可能决定“优化”长度！
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

Suggestions:
Ensure that all master-to-slave clock distribution distances are nominally identical.
Ensure that all slave-to-master data distribution distances are nominally identical.

This is easier to do with cabled links rather than backplane links. Buy and use a set of off-the-shelf cable assemblies rather than let your local, friendly wire-man make them up, as (s)he may decide to 'optimise' the lengths!

------------------------------------------
"If it don't work in simulation, it won't work on the board."

建议：确保所有主从时钟分配距离名义上相同。确保所有从站到主站的数据分配距离名义上相同。
为什么？
为什么不设计以适应不确定的偏差，并且仅仅依靠（仅）公共时基？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Suggestions:
Ensure that all master-to-slave clock distribution distances are nominally identical.
Ensure that all slave-to-master data distribution distances are nominally identical.
 
Why?  Why not design to accommodate indeterminate skews, and simply rely (only) on common timebase?
 
-- Bob Elkind
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2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

“为什么不设计以适应不确定的偏差，而只是依靠（仅）共同的时基？”因为这更难。
如果这是一次性或少量的系统，那么以牺牲更高的部件成本为代价来减少工程设计工作是有意义的（至少对我而言）。你所建议的对于生产系统来说是正确的。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

"Why not design to accommodate indeterminate skews, and simply rely (only) on common timebase?"

Because that is harder. And if this is a one-off or few-off system, then reducing engineering design effort at the expense of higher part costs make sense (at least to me).

What you are suggesting would be right for a production system.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

因为那更难。
这是更多的代码行，添加逻辑来控制IDELAY块，以相对于FPGA的全局串行速率时钟副本来校正串行数据输入。
这是Virtex-5器件的主流应用。
这消除了系统中未计入或不受控制的偏斜的不确定性。
电缆（如果有）更简单，电路板布局更简单。
总而言之，生活甚至可能更简单，无需管理歪斜或担心管理歪斜。
只是我的观点。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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你读过手册了吗？
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以下为原文

Because that is harder.
 
It's more lines of code, adding the logic to control the IDELAY blocks to deskew the serial data input with respect to the FPGA's copy of the global serial-rate clock.  This is a mainstream application for the Virtex-5 devices.
 
This removes the uncertainty of unaccounted or uncontrolled skews in the system.  Cables (if any) are simpler, and board layout is simpler. In sum, life might even be simpler without needing to manage skews or worry about managing skews.
 
Just my opinion.
 
-- Bob Elkind
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我相信你会同意，有很多好的方法可以解决大多数工程问题。
只要你选择其中一个，一切都会好的......
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

As I'm confident you will agree, there is more than one good-enough way to solve most engineering problems. And as long as you pick one of those, all will be well-enough...

------------------------------------------
"If it don't work in simulation, it won't work on the board."

嗨， 
谢谢（你的）信息。
我知道所有奴隶的时钟可以用两种方式给出：
1.主机的单个时钟输出到达所有从机，这样每个都获得相同的时钟（使用相同的长度轨道）。
这会引入时钟线上的加载吗？
2.专用时钟避免加载，这里挑战是控制主fpgas输出引脚到引脚偏斜。
该时钟也将用于从设备，为其他逻辑生成400Mhz时钟（使用DCM），因此输入时钟参数将控制此时钟精度以及所有从设备中时钟的相似性。



以下为原文

Hi,
      thanks for the info.
I understand that the clock to all the slaves can be given in 2 ways:
1. single clock output from master going to all slaves , this way each gets same clock(using same length tracks). Will this introduce loading on clock line?
2. dedicated clocks to avoid loading ,here challange is to control master fpgas output pin to pin skew.
 
This clock will also be used in slaves to generate 400Mhz clock (using DCM) for other logic hence the input clock parameters will control this clocks accuracy as well as similarity of the clock in all the slaves.
 

“这会在时钟线上引入加载吗？”如果你没有缓冲它就会出现。
赛普拉斯曾经制造合适的时钟分配缓冲器。
可能他们还是......
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

"Will this introduce loading on clock line?"
It will if you don't buffer it. Cypress used to make suitable clock distribution buffers. Probably they still do...

------------------------------------------
"If it don't work in simulation, it won't work on the board."

所以我得出结论，我需要一个时钟分配IC。



以下为原文

so shall i conclude that i need a clock distribution IC.

所以我得出结论，我需要一个时钟分配IC。
或者，您可以直接（径向）将主时钟从主站分配给每个从站。
如果你有IO引脚这样做。
你有没有提到主设备和从设备之间的定时“同步”（或耦合）需要什么？
鉴于时钟将在每个从器件上使用DCM或PLL进行再生，是否有任何有用的目的可以分配比100MHz（或50MHz）更快的时钟？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
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以下为原文

so shall i conclude that i need a clock distribution IC.
 
Or you can distribute the clock directly (radially) from the master to each of the slaves.  If you have the IO pins to do so.
 
Did you ever mention what you require for timing 'synchronisation' (or coupling) between the master and slaves?
 
Given that the clock will be regenerated with a DCM or PLL at each slave, is there any useful purpose for distributing a clock faster than 100MHz (or 50MHz, for that matter)?
 
-- Bob Elkind
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你有没有提到主设备和从设备之间的定时“同步”（或耦合）需要什么？
你能解释一下上面的陈述吗？
鉴于时钟将在每个从器件上使用DCM或PLL进行再生，是否有任何有用的目的可以分配比100MHz（或50MHz）更快的时钟？
我打算使用相同的时钟在主设备和从设备之间进行数据传输，以及生成400Mhz时钟。



以下为原文

Did you ever mention what you require for timing 'synchronisation' (or coupling) between the master and slaves?
 
Can you please explain the above statement.
 
Given that the clock will be regenerated with a DCM or PLL at each slave, is there any useful purpose for distributing a clock faster than 100MHz (or 50MHz, for that matter)?
 
i intend to use the same clock for data transfer  between master and slaves as well as for generating 400Mhz clock.

你有没有提到主设备和从设备之间的定时“同步”（或耦合）需要什么？
这是对您第一篇文章的引用。
除了可靠的数据传输之外，主站和从站之间是否还有其他（未说明的）时序要求？
鉴于时钟将在每个从器件上使用DCM或PLL进行再生，是否有任何有用的目的可以分配比100MHz（或50MHz）更快的时钟？
我打算使用相同的时钟在主设备和从设备之间进行数据传输，以及生成400Mhz时钟。
rcingham可能有一个有趣而又不同于我的方法，而rcingham完全正确地提醒我们所有人（特别是我）有一个以上可能和理性的解决方案。
换句话说 - 使用常用的美国口语 - 有一种方法可以给猫皮肤。
这是一种看似可行的方法：
主：
生成200MHz时钟，用于参考和全局逻辑系统分配，并在器件内使用。
用于以每通道400Mbit / sec速率传输和接收串行数据（使用DDR时钟模式）。
生成9个50MHz时钟的相同副本，以便分发给9个从站。
如果简单的数据传输是唯一的时序和同步要求，那么单端（而不是差分）传输就足够了。
此时钟的使用很简单且有限：为主设备和所有从设备提供公共时基。
从站：
从50MHz时基时钟（从Master接收）重新生成（使用PLL）200MHz时钟，用于参考和全局逻辑系统分配并在器件内使用。
用于串行数据的发送和接收（DDR模式）。
两个主人和奴隶：
所有这些都使用源自Master的时基参考生成的通用200MHz时基。
所有这些都以每通道400Mbits / sec的速度接收串行数据，与200MHz（本地复制）全局时钟具有不确定的相位对齐。
所有输入串行数据通道都需要使用可变延迟模式的IODELAY模块与本地200MHz时钟对齐，这需要使用IDELAYCTRL模块。
主设备和从设备之间的所有串行输入和输出数据互连将是差分对（例如LVDS_25）。
使用200MHz（DDR或半比特率）时钟和IDDR和ODDR模块，不需要使用ISERDES和OSERDES模块。
该结构可处理200MHz全局结构时钟和与IDDR和ODDR模块的内部半速率数据连接。
如果需要较低频率的全局系统时钟，则可能优选使用ISERDES和OSERDES块。
使用IODELAY块将输入串行数据与本地200MHz时钟对齐的优点是：
互连长度匹配不再是一个问题
主设备和从设备之间的热梯度不再是一个问题
每个从设备可以重新生成自己的本地串行速率时钟，从主设备锁定到时基
从主站到从站的时基分布可以是低频（低EMI），低成本（单端，单引脚）
这有意义吗？
请记住，我将100％的设计时间花在Spartan-6上，而不是Virtex（5或6），所以我可能会做出一些愚蠢和错误的假设。
- 鲍勃埃尔金德
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以下为原文

Did you ever mention what you require for timing 'synchronisation' (or coupling) between the master and slaves?
 
This is a reference to your first post.  Other than reliable data transfer, is there any other (unstated) timing requirement between the master and the slaves?
 
Given that the clock will be regenerated with a DCM or PLL at each slave, is there any useful purpose for distributing a clock faster than 100MHz (or 50MHz, for that matter)?
 
i intend to use the same clock for data transfer  between master and slaves as well as for generating 400Mhz clock.

 
rcingham may have an interesting and yet different approach than mine, and rcingham is entirely correct in reminding all of us (particularly me) that there is more than one possible and rational solution.  In other words -- to use a commonly used American colloquialism -- there is more than one way to skin a cat.  Here is an approach which seems workable:
 
MASTER:
 

• Generates 200MHz clock for reference and global logic system distribution and use within the device.  Used for transmission and reception of serial data at 400Mbit/sec rate per channel (using DDR clocking mode).
  

• Generates 9 identical copies of 50MHz clock for distribution to the 9 slaves.  If simple data transfer is the only timing and synchronisation requirement, then single-ended (rather than differential) transmission is entirely adequate.  The usage of this clock is simple and limited:  provide a common timebase for the master and all slaves.
  

 
SLAVES:
 

• Re-generates (using PLL) from 50MHz timebase clock (received from Master) a 200MHz clock for reference and global logic system distribution and use within the device.  Used for transmission and reception of serial data (DDR mode).
  

 
BOTH MASTER AND SLAVES:
 

• All are using a common 200MHz timebase generated from timebase reference sourced from the Master.
  

• All are receiving serial data at 400Mbits/sec per channel, with indeterminate phase alignment to the 200MHz (local copy) global clock.
  

• All input serial data channels will need to be aligned to the local 200MHz clock using an IODELAY block in variable delay mode, which requires the use of IDELAYCTRL block.
  

• All serial input and output data interconnect between master and slaves will be differential pairs (e.g. LVDS_25).
  

• Using a 200MHz (DDR, or half-bitrate) clock and IDDR and ODDR blocks, the use of ISERDES and OSERDES blocks isn't required.  The fabric can handle a 200MHz global fabric clock and the internal half-rate data connections to the IDDR and ODDR blocks.  If a lower frequency global system clock is desired, then using the ISERDES and OSERDES blocks may be preferred.
  

 
The advantages of using the IODELAY blocks to align the incoming serial data to the local 200MHz clock are:
 

• interconnect length matching is no longer a concern
  
• thermal gradients between master and slaves is no longer a concern
  
• each slave can re-generate its own local serial rate clock, locked to timebase from the master
  
• timebase distribution from master to slaves can be low frequency (low-EMI), lower-cost (single ended, single pin)
  

 
Does this make sense?  Keep in mind, I spend 100% of my design time in Spartan-6 land, not Virtex (5 or 6), so I may have made some silly and mistaken assumptions.
 
-- Bob Elkind
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嗨， 
谢谢你的详细解释。
是的，它可以为我的申请服务，你说的还有一个澄清
使用IODELAY块将输入串行数据与本地200MHz时钟对齐的优点是：
互连长度匹配不再是一个问题
主设备和从设备之间的热梯度不再是一个问题
每个从设备可以重新生成自己的本地串行速率时钟，从主设备锁定到时基
从主站到从站的时基分布可以是低频（低EMI），低成本（单端，单引脚）
在这里我理解IODELAY仅用于数据.50Mhz时钟（refrence）用于生成200Mhz然后有效多少是第三点“每个从设备可以重新生成自己的本地串行速率时钟，锁定到时基
大师”。



以下为原文

Hi,
      Thanks for the detailed explanation.
yes it can serve my application, just one more clarification you said
 
The advantages of using the IODELAY blocks to align the incoming serial data to the local 200MHz clock are:
 

• interconnect length matching is no longer a concern
  
• thermal gradients between master and slaves is no longer a concern
  
• each slave can re-generate its own local serial rate clock, locked to timebase from the master
  
• timebase distribution from master to slaves can be low frequency (low-EMI), lower-cost (single ended, single pin)
  

here i understand that IODELAY is used only for the data.the 50Mhz clock(refrence) is used to generate 200Mhz then the how much valid is the third point "each slave can re-generate its own local serial rate clock, locked to timebase from the master".

我不明白你的问题或疑虑。
所有8个从设备均生成（本地）200MHz时钟，该时钟频率锁定到主设备生成的50MHz时基。
IDELAY模块为每个本地200MHz时钟提供每个串行输入的相位对齐。
只要所有设备都是频率锁定的，它都可以工作。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

I don't understand your question or concern.  All 8 slave devices are each generating a (local) 200MHz clock which is frequency-locked to the 50MHz timebase generated by the master.  The IDELAY blocks provide phase alignment of each serial input to each local 200MHz clock.  As long as all the devices are frequency-locked, it all works.
 
-- Bob Elkind
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