使用DCM时132MHz时钟的占空比是否为50％

Z，
是的，CLKFX输出标称值为50％，+ /  -  5％。
抖动是由ISE中的抖动计算器向导预测的。
占空比+/- 5％规范的原因只是“正常”工艺变化，因此我们假设给定部分的占空比为47％。
另一部分可能是51％，依此类推。
在占空比的顶部，存在上述抖动，来自抽头延迟线多路复用器选择不同的抽头以获得正确的频率（每9个输入时钟22个时钟）。
如果DCM模式使用CLKFB引脚，则每9个输入时钟，输出时钟（FX）被强制（硬对齐），以便CLKIN上升沿和CLKFX上升沿对齐到+/- 100ps
。
因此，来自抖动抖动的最大“命中”发生在每9个输入时钟或每22个输出时钟。
在查看使用CLKFX的上升沿或下降沿的时序时，不要忘记抖动和占空比。
如果您有适当的约束，这应该由工具自动完成。
检查一下，并确保CLKFX时钟域的数据路径有足够的松弛。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

z,
 
Yes, the CLKFX output is nominally 50%, +/- 5%.

The jitter is as predicted by the jitter calculator wizard in ISE.
 
The reason for the +/-5% specification on duty cycle is just "normal" process variations, so let us suppose a given part is 47% duty cycle.  Another part might be 51%, and so on.
 
On top of the duty cycle, there is the jitter mentioned above, from the tapped delay line multiplexer choosing different taps to get the right freqency (22 clocks for every 9 input clocks).
 
If the DCM mode is such that the CLKFB pin is used, then every 9 input clocks, the output clock (FX) is forced (hard-aligned) so that the CLKIN rising edge, and the CLKFX rising edge align to +/- 100ps.  Thus the biggest "hit" from the tap jitter occurs every 9 input clocks, or every 22 output clocks.
 
When looking at the timing of using the rising, or falling edge of CLKFX, don't forget the jitter, and the duty cycle.  This should all get done automatically by the tools, if you have the proper constraint.  Check that you do, and that you have sufficient slack on the data paths for the CLKFX clock domain.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

Mr.Lesea，
谢谢你的快速回复！
有一些问题：
1.如果我们使用CLKFX，有什么方法可以减少偏差？
2.如果我们想让CLK2X创建一个108MHz的时钟（外部时钟也是54MHz），会有同样的问题吗？
3.为了获得132MHz时钟使用54MHz外置，有没有一个很好的方法来解决这个问题？
谢谢！



以下为原文

Mr.Lesea,
 
Thank you for your swift reply!
 
There are some questions:
1. If we use CLKFX, is there any way can reduce the deviation?
2. If we want to use CLK2X to creat a 108MHz clock ( the external clock is also 54MHz ), will have the same problem?
3. In order to get 132MHz clock use 54MHz external, is there a good way to solve this problem?
 
Thank you!

Z，1。
无法改善CLKFX抖动，除了使用更小的M，更小的D.较小的M和D值比较大的M和D值具有更少的抖动。
频率准确，没有频率偏差，只有相位噪声（抖动）2。
CLK2X的峰峰值抖动可能要小3到4倍。
此输出来自DLL部分，而不是DFS部分，它具有较少的抖动3。
CLKFX。
有几百ps的抖动p-p是个问题，为什么呢？
对于大多数设计而言，具有强大的开关输出和一个时钟域，在没有CLKFX的情况下，抖动可高达1000 ps。
如果抖动是一个问题，你必须努力工作以保持所有开关噪声低（使用时钟的不同相位来分散瞬态，使用慢速偏移，较弱的IO，使用LVDS IO等......）DCM将
是你最少的问题。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

z,

1.  No way to improve CLKFX jitter, except to use a smaller M, smaller D.  Smaller M and D values have less jitter than larger M and D values.  The frequency is exact, there is no frequency deviation, only phase noise (jitter)
2.  CLK2X has perhaps 3 to 4 times less peak to peak jitter.  This output is from the DLL part, not the DFS part, which has less jitter
3.  CLKFX.  Having a few hundreds of ps jitter p-p is a problem, why?  With strong switching outputs, and one clock domain for most of a design, jitter can be as high as 1000 ps, without the CLKFX.  If jitter is a problem, you have to work hard to keep all switching noise low (use different phases of a clock to spread out the transients, use slow skew, weaker IO, use LVDS IO, etc....)  The DCM will be the least of your probelms.Austin Lesea
Principal Engineer
Xilinx San Jose

Mr.Lesea
谢谢您的回复。
还有一个问题，以下是我们的设计： 
------> CLK +
132MHz时钟---> OBUFDS- |
======> DDR2芯片 
------> CLK-
我们发现CLK +的占空比为48％，CLK-的占空比为43％，因此，交叉点存在一些问题。
附件是一个波形。
我们怎样才能解决这个问题。
谢谢！！！



以下为原文

Mr.Lesea
 
Thank you for your reply.
 
There is another question, following is our design:
 
                                                    ------>CLK+
132MHz clock --->OBUFDS-|                        ======> DDR2 Chip
                                                    ------>CLK-
 
We found that the duty cycle of the CLK+ is 48% and the duty cycle of CLK- is 43%, because of this, the cross point have some problems. 
 
Attachment is a waveform.
 
How can we tackle this problem.
 
Thank you!!!

我们发现CLK +的占空比为48％，CLK-的占空比为43％，因此，交叉点存在一些问题。
由于“逻辑阈值”偏移，负载不匹配，输出驱动电平不匹配，示波器探头不匹配，示波器探头接地技术和示波器输入不匹配，您的测量方法极易受到失真的影响。
换句话说，您在示波器波形显示上看到的某些占空比不匹配可能是真实的，其中一些可能由您的测量技术和设备引入（并且不存在于信号中）。
您是否尝试通过将两个示波器探头放在同一信号上来重复波形显示（不要移动示波器探头GND连接点，只需将一个探头移动到与另一个探头相同的信号）？
如果示波器，探头和GND技术是完美的，并且两个示波器探头位于信号走线的相同位置，则两个波形应完全相同且重叠。
您可以通过在迹线上的其他位置移动一个探头，通过更改GND附件，通过切换示波器输入通道，通过更改示波器中的垂直偏移等来引起差异（改进和失真）等。
我们怎样才能解决这个问题。
简单：差分输出和差分接收器。
单端接收器适用于单相（单有效边沿）时钟。
DDR（两个有效边沿）时钟需要差分信号，以消除单端信号的固有脉冲收缩/增长敏感性。
差分信令的好处产生并应用于数据信号和时钟信号。
一些“技术”通过“花费”额外的引脚和电路板在时钟上运行而不是数据信号。
这种折衷方法的一个突出例子是DDR2 DRAM。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

We found that the duty cycle of the CLK+ is 48% and the duty cycle of CLK- is 43%, because of this, the cross point have some problems. 
 
Your measurement method is highly susceptible to distortion due to 'logic threshold' offset, loading mismatch, output drive level mismatch, scope probe mismatch, scope probe grounding technique, and scope input mismatch.  In other words, some of the duty cycle mismatch you 'see' on the scope waveform display may be real, some of it may be introduced by your measurement technique and equipment (and is not present in the signals).
 
Have you tried repeating your waveform display by having both scope probes on the same signal (don't move the scope probe GND attachment points, just move one probe to the same signal as the other probe)?  If your scope, probes, and GNDing technique are perfect, and the two scope probes are at the same position of the signal trace, the two waveforms should be completely identical and overlapping.
 
You can induce differences (improvements and distortions) by moving one probe elsewhere on the trace, by changing GND attachment, by switching scope input channel, by changing vertical offset in the scope, etc. etc.
 
How can we tackle this problem.
 
Simple:  Differential output and differential receivers.  Single-ended receivers are fine for single-phase (single active edge) clocks.  DDR (two active edge) clocks need differential signaling to eliminate the inherent pulse shrinkage/growth susceptibility of single-ended signaling.

The benefits of differential signaling accrue and apply to data signals as well as clock signals.  Some 'technologies' compromise by 'spending' the extra pins and circuit board runs on the clocks, but not the data signals.  One prominent example of this compromise approach is DDR2 DRAM.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

上图是DDR2差分时钟的设计。
当DCM2和DCM3的DUTY_CYCLE_CORRECTION设置为TRUE时，无论如何都会改变DCM3的“相移”，总会出现波形交叉点的问题，如下所示：
CH1：CLK_P; CH2：CLK_N
当DCM2和DCM3的DUTY_CYCLE_CORRECTION设置为FALSE时，适当重新调整DCM3的相移可以得到如下的完美波形：
CH1：CLK_P; CH2：CLK_N
那么，问题：
1. DUTY_CYCLE_CORRECTION的作用和影响因素是什么;
2.当DUTY_CYCLE_CORRECTION设置为TRUE时，存在交叉点问题，当设置为FALSE时，问题解决了，为什么？
这会改变其他问题吗？ 
谢谢！



以下为原文


The above figure is  our design of DDR2 Differential Clock.
When DUTY_CYCLE_CORRECTION of DCM2 and DCM3 are set TRUE, in any case change the "phase shift" of DCM3, there is always a problem of cross-point of the waveform , as shown follows:

CH1:Clk_p;Ch2:Clk_n
 
When the DUTY_CYCLE_CORRECTION of DCM2 and DCM3 are set to FALSE, appropriate readjustment the phase shift of DCM3 can get a perfect waveform as follows:

CH1:Clk_p;CH2:Clk_n
 
So, the questions:
1.What is the role of DUTY_CYCLE_CORRECTION and the affection to clock;
2.When the DUTY_CYCLE_CORRECTION is set TRUE, there is a problem of cross-point, when it set to FALSE, the problem is solved, why?
3.Will this change bring other problems?
                                                                                         Thank you!

z，你的信号完整性或测量设置非常糟糕，你根本不知道任何事情。直到你有清晰的边缘，以及设备提供的上升和下降时间，你甚至不能“
请参阅“或完全按照任何精度测量工作循环，
Austin Lesea主要工程师Xilinx San Jose



以下为原文

z,

Your signal integrity, or measurement setup iss so bad, you don't know anything about anything at all.

Until you have nice crisp edges, and rise and fall times that are actually what the device delivers, you can't even "see" or measure the duty cycle with any accuracy at all,

Austin Lesea
Principal Engineer
Xilinx San Jose

Mr.Lesea，
再次感谢您的快速回复。
以上波形由我们的日本客户使用20GS / s示波器测量，
我们不知道他们使用的具体测量方法，所以可能存在一些问题。
我们将继续与客户沟通。
你能详细解释一下DUTY_CYCLE_CORRECTION的作用是什么吗？
谢谢！



以下为原文

Mr.Lesea,
 
Thanks again for your quick reply.
 
The waveform above is measured by our Japanese customers with a 20GS/s oscilloscope,
we do not know the specific measurement methods they used, so there maybe some problems.
 
We will continue to communicate with customers.
 
Can you explain what is the role of DUTY_CYCLE_CORRECTION in details?
 
Thank you!

z，如果这是日本的客户，你需要提交一个webcase，并要求日本的Xilinx FAE帮助解决问题......这不会发生在这个论坛！占空比校正纠正了工作周期
DCM的输出为+/- 5％。
除非过程偏斜（nmos强于/弱于pmos），否则占空比开启或关闭都不会产生差异（甚至可能不需要校正，通常也不需要校正）。如果采用20 GS / S进行测量（已发布）
范围已低通滤波：探测范围错误，设置错误，或者在长电缆末端测量。
在任何情况下，根本无法诊断任何东西。而且，该图片是使用2.5 GS / S范围（图片右侧）拍摄的，这仍然足够快，因此测量技术非常错误，或者
设置。此外，迹线不适用于差分标准：2.8v不是LVDS！
因此，它看起来甚至看起来都不是来自差分标准输出，在这种情况下，所有的赌注都是完全的。
如果这是来自单端标准，如3.3v LVCMOS，那么另一个引脚如何在另一个引脚上产生？
不使用差分标准会导致生成和维护任何占空比变得困难（FPGA中的导线延迟导致IOB，引脚上的负载，从FPGA到负载的传输线......）。打开一个webcase。
请求日本FAE。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

z,

If this is a customer in Japan, you need to file a webcase, and request a Xilinx FAE in Japan to help solve the problem....it is not going to happen in this forum!

Duty cycle correction corrects the duty cycle of the output of the DCM to within +/- 5%.  Unless the process is skewed (nmos is stronger/weaker than pmos) duty cycle on or off will make no difference (correction may not even be necessary, and often is not).

That measurement (posted) if taken with a 20 GS/S scope has been low pass filtered:  either the wrong scope probes, the wrong settings, or it is measured at the end of a long cable.  In any event, it is useless to diagnose anything at all.

And, that picture is taken with a 2.5 GS/S scope (right on the picture) which is still fast enough, so something is very very wrong with the measurement techniques, or the setup.

Also, the traces are not for a differential standard:  2.8v is NOT LVDS!  So, it doesn't even look like it is from a differential standard output, it which case, all bets are off, totally.  If this is from a single ended standard, like 3.3v LVCMOS, then how is the other phase generated on the other pin?  Not using a differential standard makes generating and maintaining any duty cycle gets difficult (delays in the wires in the FPGA leading to the IOB, loading on the pin, transmission line from the FPGA to the load...).

Open a webcase. request Japanese FAE.





Austin Lesea
Principal Engineer
Xilinx San Jose

此外，迹线不适用于差分标准：2.8v不是LVDS！
因此，它看起来甚至看起来都不是来自差分标准输出，在这种情况下，所有的赌注都是完全的。
奥斯汀，
从帖子＃5开始：
还有一个问题，以下是我们的设计： 
------> CLK +
132MHz时钟---> OBUFDS- |
======> DDR2芯片 
------> CLK-
基于此，我猜测输出是差分的，并且使用的IOSTANDARD是DIFF_SSTL18_x之一。
如果没有端接，输出信号摆幅是否可能是轨到轨（例如1.8V）？
并且，该图片是使用2.5 GS / S示波器（图片右侧）拍摄的，这仍然足够快，因此测量技术或设置非常错误。
你指的是在＃5后发布的波形。
绝对同意，这些测量完全没有价值。
然而，＃7后的波形看起来完全合理。
信号摆幅为1.8V。
你怎么看？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
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以下为原文

Also, the traces are not for a differential standard: 2.8v is NOT LVDS! So, it doesn't even look like it is from a differential standard output, it which case, all bets are off, totally.
 
Austin,
 
From post #5 in this thread:
 
There is another question, following is our design:
 
                                                    ------>CLK+
132MHz clock --->OBUFDS-|                        ======> DDR2 Chip
                                                    ------>CLK-

Based on this, I'm guessing that the outputs are differential, and the IOSTANDARD used is one of the DIFF_SSTL18_x.  If unterminated, is it possible the output signal swings are rail to rail (e.g. 1.8V)?
 
And, that picture is taken with a 2.5 GS/S scope (right on the picture) which is still fast enough, so something is very very wrong with the measurement techniques, or the setup.
 
You are referring to the waveforms posted in post #5.  Absolutely agreed, these measurements are completely worthless.  The waveforms in post #7 look entirely reasonable, however.  Signal swings are 1.8V.  What do you think?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

鲍勃，
谢谢你指出这一点。
至于差分SSTL 1.8伏信号，这是一个标准，如果是这样的话。
这是什么部分？
V6？
V5？
它看起来不是正确的术语（从+到 -  100欧姆）....这里的东西仍然非常错误。
如果是V5或V6，则存在差分SSTL。
鉴于此，如果不使用DDR IOB DFF，则无法保证占空比（仅将时钟传递给IO引脚不是获得良好波形的方法：必须使用DDR IOB DFF，如图所示）
获得50/50方波的指南）。
当然，还有测量设置的潜在问题吗？
他们是否使用相同的探头（相同的探头），是否将其设置为差分测量（否）？
看起来他们正在测量两个单端信号.....
具有真正差分的示波器图像，两个单端，一次全部，以及显示一些时间参考的第四条迹线（使用的原始系统时钟，或者我们可以比较的其他东西）怎么样？
我的建议是在工作中，在客户现场找到合适的人，说出他们的语言！
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Bob,
 
Thanks for pointing that out to me.
 
As for the Differential SSTL 1.8 volt signal, that is a standard, if that is what it is.  What part is this?  V6?  V5?  Doesn't look like it is properly termoinated (100 ohms from + to -)....something is still very very wrong here.
 
If V5 or V6, yes there is differential SSTL.  Given that, if the DDR IOB DFF's are not used, then there is no guarantee of duty cycle (just passing a clock to an IO pin is NOT the way to get a good waveform:  one must use the DDR IOB DFF's as shown in the guides to get a 50/50 square wave).
 
Then, of course, there are measurement setup potential issues?  Did they use the same probes (identical probes), did they set it up for differential measurement (no)?  Looks like they are measuring two single ended signals.....
 
How about a scope picture with true differential, AND two single ended, all at once, along with a fourth trace showing some time reference (the original system clock used, or something else that we can compare against)?
 
My suggestion is to get the right people, on the job, at the customer site, speaking their language!
 
 
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

如果是V5或V6，则存在差分SSTL。
鉴于此，如果不使用DDR IOB DFF，则无法保证占空比（仅将时钟传递给IO引脚不是获得良好波形的方法：必须使用DDR IOB DFF，如图所示）
获得50/50方波的指南）。
致ZHC，
我怀疑在FPGA内部，任何被驱动和接收单端而非差分的信号都容易受到占空比失真的影响，也称为“脉冲收缩和增长”，原因如下： 
逻辑阈值和信号摆幅之间的偏移
信号驱动器的不对称性
这些因素虽然在实际环境中很小，但仍然是不可避免的。
DDR2必须回答的问题是DQ信号与DQS选通（即偏斜）的对齐。
特别是对于低频系统（133MHz），这比紧凑的占空比控制更为关键。
确保DQ和DQS时序匹配的最简单实现是使用相同的输出结构。
正如Austin建议的那样，使用ODDR模块可以实现DQ和DQS信号输出。
如果占空比控制仍然是一个问题，即使在133MHz，解决这个问题的严格方法是在266MHz而不是133MHz运行输出逻辑。
对于DQ和DQS信号，您将在单数据速率配置而不是DDR中使用IOB寄存器。
50％的占空比偏差应接近差分时钟和DQS输出的不可测量，差分测量。
-  Bob Ekind
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以下为原文

If V5 or V6, yes there is differential SSTL.  Given that, if the DDR IOB DFF's are not used, then there is no guarantee of duty cycle (just passing a clock to an IO pin is NOT the way to get a good waveform:  one must use the DDR IOB DFF's as shown in the guides to get a 50/50 square wave).
 
To ZHC,
 
I suspect that internal to the FPGA, any signal which is driven and received single-ended rather than differentially is susceptible to duty cycle distortion, also call 'pulse shrinkage and growth', due to:

• offset between logic threshold and signal swing
  
  
• asymmetry in signal driver
  

These factors, as small as they are in a practical context, are still unavoidable.
 
The question which must be answered for DDR2 is alignment of DQ signals to DQS strobe (i.e. skew).  Particularly with a low frequency system (133MHz), this is more critical than tight duty cycle control.  The simplest implementation which ensures matching of DQ and DQS timing is to use identical output structures.  Using ODDR blocks, as Austin suggests, for both DQ and DQS signal outputs will accomplish this.
 
If the duty cycle control is still a concern, even at 133MHz, the rigorous approach for solving this is to run the output logic at 266MHz rather than 133MHz.  You will be using IOB registers, in single data rate configuration rather than DDR, for both DQ and DQS signals.  Duty cycle deviation from 50% should be close to unmeasurable on the differential clock and DQS outputs, measured differentially.
 
-- Bob Ekind

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