是否可以使用单个DCM生成2x和4x时钟？

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是的你可以...
DCM模块有一个2x端口，因此如果您输入50 MHz时钟，您将得到100 MHZ，以及一个端口CLK_FX，您可以设置输出频率。
您是否正在尝试编写和阅读spartan3e入门套件的DDR？



以下为原文

Yes you can...
the DCM module has a 2x port so if you have in input a 50 MHz clock , you get 100 MHZ, and a port CLK_FX which you can set the output frequency.
 
Are you trying to write and read on DDR of spartan3e Starter kit?

谢谢！
是的，目标是访问S3e入门套件上的SDRAM。
200 MHz时钟是我尝试使用的设计所需的270度移位100MHz时钟的替代方案。
克劳斯



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Thanks! Yes, the goal is to access the SDRAM on the S3e starter kit.
The 200 MHz clock is the alternative to the 270 degree shifted 100MHz clock required by the design I am trying to use.
Klaus

嗨克劳斯，
向我发送有关您项目状态的信息，我也很感兴趣;
如果您需要，请与我联系。
现在我正在为以太网芯片开发MAC控制器。
你见过MIG发电机吗？



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Hi Klaus,
 
send me information on status of your project, I'm interested too; if you need,contact me.
 
Now I'm developing the MAC controller for the the ethernet chip.
 
Have you seen the MIG generator?
 

核心***VHDL源没有问题，但ISE模拟器根本没有在CLKFX输出端显示4x时钟。
CLK0和CLK2X都可以。
什么缺少的想法？
这是一个错误吗？
克劳斯



以下为原文

The core generator provided the VHDL source without a problem, but the ISE simulator does not show the 4x clock at the CLKFX output at all. CLK0 and CLK2X are ok.
Any ideas what is missing? Is this a bug?
Klaus

rindtorff写道：核心生成器提供VHDL源没有问题，但ISE模拟器根本没有显示CLKFX输出的4x时钟。
CLK0和CLK2X都可以。
什么缺少的想法？
这是一个错误吗？ 
是否所有DCM实例的INIT都设置为正确和期望的值？
-一个
----------------------------是的，我这样做是为了谋生。



以下为原文

rindtorff wrote:
The core generator provided the VHDL source without a problem, but the ISE simulator does not show the 4x clock at the CLKFX output at all. CLK0 and CLK2X are ok.
Any ideas what is missing? Is this a bug?

Are all of the DCM instance's INITs set to the correct and desired values?
 
-a
----------------------------Yes, I do this for a living.

尝试这个。
我还添加了一个测试平台，以便您可以看到如何使用dcm模块。
如果要在项目中使用dcm，请参阅如何在top_level.vhd上实例化模块
最好的祝福
Alexgiul
dcm.rar 79 KB



以下为原文

Try this.
 
 
I  added also a test bench so you can see how use dcm module.
 
If you want to use dcm in your project see how I have instantiate the module on top_level.vhd
 
Best Regards
 
Alexgiul
 
 
            dcm.rar ‏79 KB

我当然希望如此，这是由核心生成器创建的。
看来源，似乎没问题。
有两个时钟频率可用。
克劳斯



以下为原文

I sure hope so, this was created by the core generator. Looking at the source, it seems to be fine. Two of the clock frequencies are available.Klaus

谢谢Alexgiul，你的代码工作了。
但是，一旦我将时钟反馈更改为“2X”，它在模拟器中也会失败。
我能够使用ISE 10.1.02（nt）一致地重现该问题。
只要（1）时钟反馈设置为“2X”*或*（2），核心发生器中的时钟反馈设置为“外部”，模拟就会失败。
CLKFX停留在'0'且CLK2X错误（频率相同，但H / L比率为25％，与其他所有脉冲一样丢失。）
克劳斯



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Thanks Alexgiul, your code worked. However, as soon as I changed the clock feedback to "2X" it fails as well in the simulator.
I was able to reproduce the problem consistently with ISE 10.1.02 (nt). As soon as (1) either the clock feedback is set to "2X" *or* (2) the clock feedback is set to "External" in the core generator, the simulation fails. CLKFX is stuck at '0' and CLK2X is wrong (same frequency, but H/L ration of 25%, like every other pulse is missing.)
Klaus

我很乐意帮助fpga开发人员!!!!
很多时候，我在这个论坛上发帖提问，希望有人回复我。
我有一个问题：您是否尝试过实施DDR控制器？
我的问题是在UCF文件中，某些约束是“错误的”（对于ISE） - 我正在使用MIG 2.0



以下为原文

I'm very glad to help fpga developer!!!!
A lot of time, I post questions on this forum and I hope that someone reply to me.
 
I have a question : have you try to implement the DDR controller ?
my problem is on the UCF file where some constraint are "wrong" (for ISE)  - I'm using MIG 2.0

经过一些实验后，在我看来，每当我使用2x进行时钟反馈时，至少设计将无法正确模拟。
不能说合成，因为我的设计可能仍然有错误。
我通过使用两个DCM解决了我的问题，第一个从板载50MHz产生100MHz，第二个产生0（SD_CK_P），180（SD_CK_N）和270（DDR控制器）度移位时钟。
VHDL最初由coregen生成，然后由我修改。
生成的额外逻辑负责复位逻辑。
这至少在模拟中工作得很好，但是我用它驱动的DDR控制器还没有工作。
克劳斯



以下为原文

After some experimenting it seems to me that whenever I use 2x for clock feedback at least the design will not simulate properly. Can't say for the synthesis as my design probably still has errors.
I solved my issue by using two DCMs, the first generating 100MHz from the onboard 50MHz, the second generating the 0 (SD_CK_P), 180 (SD_CK_N), and 270 (DDR controller) degree shifted clocks.
The VHDL was generated initially by coregen, then modified by me. The generated extra logic takes care of the reset logic.
This works fine at least in simulation, however the DDR controller that I am driving with this doesn't work yet.
Klaus

rindtorff写道：经过一些实验，在我看来，每当我使用2x进行时钟反馈时，至少设计将无法正确模拟。
不能说合成，因为我的设计可能仍然有错误。
我通过使用两个DCM解决了我的问题，第一个从板载50MHz产生100MHz，第二个产生0（SD_CK_P），180（SD_CK_N）和270（DDR控制器）度移位时钟。
VHDL最初由coregen生成，然后由我修改。
生成的额外逻辑负责复位逻辑。
这至少在模拟中工作得很好，但是我用它驱动的DDR控制器还没有工作。
这是一个已知的BUG。
我在5月份重新打开了WebCase 739101，因为在从ModelSim XE 6.2g更新到6.3c（当前版本）后，工作模拟失败，因为DCM无法锁定。
我被告知这将用SP2修复，但事实并非如此。
Xilinx支持人员给我发了一个热补丁补丁（附件），但也没有用。
所以，不，你不是疯了：当反馈来自2X时钟时，仿真模型不会锁定。
解决方法是将CLK0输出到缓冲器然后进入CLKFB并将DCM_SP上的CLK_FEEDBACK通用更改为“1X”。
当然，它浪费了一个BUFGMUX ......
----------------------------是的，我这样做是为了谋生。
dcm_sp.vhd 60 KB



以下为原文

rindtorff wrote:
After some experimenting it seems to me that whenever I use 2x for clock feedback at least the design will not simulate properly. Can't say for the synthesis as my design probably still has errors.
I solved my issue by using two DCMs, the first generating 100MHz from the onboard 50MHz, the second generating the 0 (SD_CK_P), 180 (SD_CK_N), and 270 (DDR controller) degree shifted clocks.
The VHDL was generated initially by coregen, then modified by me. The generated extra logic takes care of the reset logic.
This works fine at least in simulation, however the DDR controller that I am driving with this doesn't work yet.

This is a KNOWN BUG. I opened WebCase 739101 back in May because after updating from ModelSim XE 6.2g to 6.3c (the current version), a working simulation failed because the DCM would not lock. I was told that this would be fixed with SP2 but it was not. The Xilinx support person sent me a hot-fix patch (attached) that also doesn't work.
 
So, no, you're not crazy: the simulation model does not lock when the feedback is from the 2X clock.
 
A workaround is to take the CLK0 out into a buffer then into CLKFB and change the CLK_FEEDBACK generic on the DCM_SP  to "1X." Sure, it wastes a BUFGMUX ...
 
 
----------------------------Yes, I do this for a living.            dcm_sp.vhd ‏60 KB

我也试图访问Spartan 3E开发板DDR芯片，但这个任务对我来说似乎太复杂了。
我将基于cpld的zx-spectrum克隆转移到这个fpga：www.zxbada.bbk.org/badaloc_fpgabut卡在外部ram上。
该机器可以作为16K频谱正常工作，并且已经能够使用bram执行具有SD卡快照功能的badaloc bootrom。
MIG（ise 10.1）生成了一个vhdl代码，它看起来比整个项目更大。
我唯一的目标是能够尽快访问ddr芯片作为具有地址总线，8位数据总线（Z80处理器）和CS，WE，OE的异步芯片。
我一直在寻找一个解决方案，但我担心我将不得不添加一个真正的静态RAM芯片。
如果有人有任何建议，请告诉我。
顺便说一句，你可以发布任何xilinx fpga板制造商的网址吗？
一个很好的解决方案就是在那里使用静态ram捕捉板子......
非常感谢！
亚历山德罗



以下为原文

I'm trying to access the Spartan 3E development board DDR chip as well, but the task seems too complicated to me.
 
I'm porting my cpld-based zx-spectrum clone to this fpga: www.zxbada.bbk.org/badaloc_fpga but got stuck at the external ram. The machine properly works as a 16K spectrum and is already able to execute the badaloc's bootrom with sd-card snapshot capabilities, just using bram.
 
The MIG (ise 10.1) generated a vhdl code which looks larger than the entire project.
 
My only goal would be being able to access the ddr chip as fast as possible as an asynchronous chip with addres***us, 8 bit databus (Z80 processor) and CS,WE,OE. I've been searching for a while for a solution but I'm afraid I will have to add a real static ram chip.
 
If someone have any advice, please let me know.
 
Btw, may you post the url of any xilinx fpga board manufacturers? A good solution would be catching a board with static ram already there...
 
Thanks a lot!
Alessandro
 

看这个！
https://roulette.das-labor.org/bzrtrac/
我已经尝试过，但从来没有让它工作，但我一直与作者联系，它应该在500E och 1600E工作，梯子是我的主卡。它可能是我，所以我会尝试它
再来一次。
希望这可以帮助！
Spectrum-clone的工作很棒！
我只是喜欢这些Emulator / CLone系统！
它是否真的有效，所以可以从卡上的图像启动游戏？
听起来很有趣，我已经建立了自己的额外主板，名为“ArcadeExtender”，带有立体声，4096色VGA，SD卡，MIDI输入，额外的PS / 2连接器和9针经典Atari Joystick连接器，其中一些很可能
会派上用场的。
最好的祝福
Magnus Wedmark



以下为原文

Look at this!
 
https://roulette.das-labor.org/bzrtrac/
 
I've tried it but never got it to work, but I've been in contact with the author and it should be working both with 500E och 1600E, the ladder is my main card.It is probably me, so I will try it again in the future.
 
Hope this helps! Nice job with the Spectrum-clone! I just love these Emulator/CLone systems! Is it really working so one can boot games from images on the card? Sounds fun, I have built my own extra board dubbed "ArcadeExtender" with Stereo sound, 4096-color VGA, SD-Card, MIDI-in, extra PS/2 connector and a 9-pin classic Atari Joystick connector some of which which probably will come in handy.
 
Best Regards
Magnus Wedmark