设计中的LUT3单元缺少输入引脚I0上的连接

嘿，我跟踪并检查了合成原理图中的信号，发现由于修剪了未使用的逻辑，连接被删除了。我找到了解决方案。谢谢，Vinay
在原帖中查看解决方案



以下为原文

Hey,

I traced and checked the signal in the synthesized schematics and found that the connection was removed due to the trimming of unused logic.
I have found the solution.

Thanks,
VinayView solution in original post

@vinay_shenoy，
您使用的是哪个vivado版本？
请检查以下答案记录，看看是否有帮助：
https://www.xilinx.com/support/answers/70111.html
您需要在xdc中应用以下约束：
set_property DONT_TOUCH true [get_cells i_design_1 / design_1_i / uhdsdi_gt_wrapper / uhdsdi_gt / uhdsdi_gt_0 / inst / gt_ch_cpllrefclksel_i_inferred_i_1]
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
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以下为原文

@vinay_shenoy,
 
Which vivado version are you using? Please check the following answer record and see if it helps:
https://www.xilinx.com/support/answers/70111.html 
 
You need to apply the following constraint in your xdc: 
set_property DONT_TOUCH true [get_cells i_design_1/design_1_i/uhdsdi_gt_wrapper/uhdsdi_gt/uhdsdi_gt_0/inst/gt_ch_cpllrefclksel_i_inferred_i_1]
 
--Syed
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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嗨，我尝试通过包含上面的set_property参数进行编译，我没有看到任何改进。
错误仍然存​​在。我正在使用Vivado 18.1版本请让我知道任何解决这个问题的方法，Vinay



以下为原文

Hi,

I tried compiling by including above set_property parameter and I don't see any improvements. The error still remains.

I am using Vivado 18.1 version

Please let me know any solution to this problem

Regards,
Vinay

@vinay_shenoy，
检查日志文件并查看是否已考虑DONT_TOUCH约束。
如果不考虑约束，那么您将看到严重警告。
你可以共享后期综合dcp文件来调试问题吗？
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@vinay_shenoy,
 
Check the log file and see if the DONT_TOUCH constraint has considered. If the constraint is not considered then you will see Critical warning. 
 
Can you share the post synthesis dcp file to debug the issue?
 
--Syed 
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
---------------------------------------------------------------------------------------------

嘿，我跟踪并检查了合成原理图中的信号，发现由于修剪了未使用的逻辑，连接被删除了。我找到了解决方案。谢谢，Vinay



以下为原文

Hey,

I traced and checked the signal in the synthesized schematics and found that the connection was removed due to the trimming of unused logic.
I have found the solution.

Thanks,
Vinay

@vinay_shenoy，
感谢更新。
在问题得到解决后，请通过标记提供解决方案的帖子“接受为解决方案”来关闭此主题。
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@vinay_shenoy,
 
Thanks for the update. As the issue is resolved, please close this thread by marking the post which has provided the solution as "Accept as solution"
 
--Syed
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
---------------------------------------------------------------------------------------------