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我有一个输入“data_in”，“rst”和“clk”的函数。
我想要做的是我想修复所有这些路线。 按照UG903中的示例，我首先尝试修复“data_in”。 但我有下面的错误。 错误：[Designutils 20-949]在net data_in上找不到驱动程序。 .xdc看起来像 set_property BEL C5LUT [get_cells r5_i_1] set_property BEL G6LUT [get_cells r3_i_2] set_property BEL H6LUT [get_cells r8_i_1] set_property BEL C6LUT [get_cells r4_i_1] set_property BEL H6LUT [get_cells data_out_INST_0] set_property BEL B5LUT [get_cells r7_i_1] set_property LOC SLICE_X53Y443 [get_cells r8_i_1] set_property LOC SLICE_X53Y442 [get_cells r4_i_1] set_property LOC SLICE_X53Y443 [get_cells r3_i_2] set_property LOC SLICE_X53Y442 [get_cells r7_i_1] set_property LOC SLICE_X53Y442 [get_cells r5_i_1] set_property LOC SLICE_X53Y442 [get_cells data_out_INST_0] set_property LOCK_PINS {I0：A3} [get_cells r4_i_1] set_property LOCK_PINS {I0： A3} [get_cells r5_i_1] set_property LOCK_PINS {I2：A1} [get_cells r8_i_1] set_property LOCK_PINS {I4：A4} [get_cells r7_i_1] set_property LOCK_PINS {I5：A4} [get_cells data_out_INST_0] set_property LOCK_PINS {I5：A5} [get_cells r3_i_2] set_property FIXED_ROUTE {{{EE1_E_BEG0 INT_NODE_IMUX_62_INT_OUT1 IMUX_W1} INT_NODE_SDQ_49_INT_OUT1 {NN1_W_BEG1 INT_NODE_IMUX_34_INT_OUT1 BOUNCE_W_2_FT1 INT_NODE_IMUX_58_INT_OUT1 IMUX_W38} SS1_W_BEG1 {INT_NODE_IMUX_63_INT_OUT0 {BYPASS_W3 INT_NODE_IMUX_44_INT_OUT0 IMUX_W37} IMUX_W23} INT_NODE_IMUX_62_INT_OUT1 IMUX_W16}} [get_nets DATA_IN] 有什么建议吗？ 以上来自于谷歌翻译 以下为原文 I have a function that has an input of "data_in", "rst", and "clk". What I want to do is that I want to fix all these routes. Following the example in UG903, I am trying to fix the "data_in" first. But I've got the error below. ERROR: [Designutils 20-949] No driver found on net data_in. The .xdc looks like set_property BEL C5LUT [get_cells r5_i_1] set_property BEL G6LUT [get_cells r3_i_2] set_property BEL H6LUT [get_cells r8_i_1] set_property BEL C6LUT [get_cells r4_i_1] set_property BEL H6LUT [get_cells data_out_INST_0] set_property BEL B5LUT [get_cells r7_i_1] set_property LOC SLICE_X53Y443 [get_cells r8_i_1] set_property LOC SLICE_X53Y442 [get_cells r4_i_1] set_property LOC SLICE_X53Y443 [get_cells r3_i_2] set_property LOC SLICE_X53Y442 [get_cells r7_i_1] set_property LOC SLICE_X53Y442 [get_cells r5_i_1] set_property LOC SLICE_X53Y442 [get_cells data_out_INST_0] set_property LOCK_PINS {I0:A3} [get_cells r4_i_1] set_property LOCK_PINS {I0:A3} [get_cells r5_i_1] set_property LOCK_PINS {I2:A1} [get_cells r8_i_1] set_property LOCK_PINS {I4:A4} [get_cells r7_i_1] set_property LOCK_PINS {I5:A4} [get_cells data_out_INST_0] set_property LOCK_PINS {I5:A5} [get_cells r3_i_2] set_property FIXED_ROUTE { { EE1_E_BEG0 { INT_NODE_IMUX_62_INT_OUT1 IMUX_W1 } INT_NODE_SDQ_49_INT_OUT1 { NN1_W_BEG1 INT_NODE_IMUX_34_INT_OUT1 BOUNCE_W_2_FT1 INT_NODE_IMUX_58_INT_OUT1 IMUX_W38 } SS1_W_BEG1 { INT_NODE_IMUX_63_INT_OUT0 { BYPASS_W3 INT_NODE_IMUX_44_INT_OUT0 IMUX_W37 } IMUX_W23 } INT_NODE_IMUX_62_INT_OUT1 IMUX_W16 } } [get_nets data_in] Any suggestion? 
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2个回答
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@ moon5756，
你能告诉我们错误信息中提到的data_in net的原理图吗？ 命令“get_property ROUTE [get_netsdata_in]”的结果是什么 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @moon5756, Can you show us the schematic of data_in net mentioned in error message? What is the result of command "get_property ROUTE [get_nets data_in]" --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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@syedz谢谢你的回复！
我有 get_property ROUTE [get_nets data_in] {} 这是什么意思？ 因此，为了进一步解释，我想要实现这一目标的主要原因是我希望删除OOC实现中的“顶级实现”过程：http：//www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug946-vivado- 分层设计tutorial.pdf。 route_design在顶层有“顶级实现”，但我相信这个过程在理论上是不必要的。 通过在pblock边界上手动路由网络，我们应该可以跳过此过程。 谢谢！ 以上来自于谷歌翻译 以下为原文 @syedz Thanks for the reply! I've got get_property ROUTE [get_nets data_in] {} what does it mean? So, to explain further, the main reason I want to achieve this is that I want to remove "top implementation" process in OOC implementation in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug946-vivado-hierarchical-design-tutorial.pdf. There is "top implementation" to route_design on the top-level, but I believe this process is theoretically unnecessary. By manually routing the nets on the pblock boundary, we should be able to skip this process. Thanks! |
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