[问答]

流水线基元时出错

问答对人有帮助，内容完整，我也想知道答案 0 大家好我是使用实例化基元的管道连接的新手我实现了一个完整的组合设计，其中我实例化了LUT和carry4瞬间，然后我在顶层实体的输入端口注册了两个寄存器级的所有输入和输出，在顶层实体输出处注册了两个寄存器级，然后我启用了寄存器平衡和检查优化实例化的预置。合成过程正确传递但是当我运行翻译过程时，错误出现与实例化的LUT相关这是错误：错误：NgdBuild：455 - 逻辑网络“Add_Rnd / Correct_B”有多个驱动程序：块Add_Rnd / Correct_B1上的引脚O，类型为LUT5，引脚PAD上的块为Add_Rnd / Correct_B，类型为PAD 错误：NgdBuild：924 - 输入焊盘网'Add_Rnd / Correct_B'驱动非缓冲原语：块状地址为Add_Rnd / DigitSum / LUT4_inst上的引脚I1，类型为LUT4，引脚I1位于块Add_Rnd / DigitSum / LUT5_inst上，类型为LUT5，引脚O开启块类型为LUT5的Add_Rnd / Correct_B1，类型为LUT6的块Add_Rnd / SelectS0OrS1227上的引脚I2，类型为LUT6的块Add_Rnd / SelectS0OrS1113_F上的引脚I2，类型为LUT6的块Add_Rnd / SelectS0OrS1113_G上的引脚I3 我是否需要实例化一个额外的组件，以便该工具可以管道这些LUT？!!!!!! 我还在层次结构中实现了一个较小的实体，我在其中实例化LUT并且没有出现此错误..那么为什么这会发生在顶级设计实体中？恐怕这是工具的一个bug :( 我使用的是ISE12.1 先谢谢了以上来自于谷歌翻译以下为原文 Hi all I am new with using the pipelinning of instantiated primitives I have implemented a full combination design in which i instantiated LUT's and carry4 instants then i registered all inputs and outputs with two register stages at input ports of the top entity and two register stages at the top entity outputs then i enabled the register balancing and checked the optimize instantiated premitives. the syntyhesis process passed correctly but when i run the translate process an Error appears related to the instantiated LUT's and here is the Error : ERROR:NgdBuild:455 - logical net 'Add_Rnd/Correct_B<10>' has multiple driver(s): pin O on block Add_Rnd/Correct_B<10>1 with type LUT5, pin PAD on block Add_Rnd/Correct_B<10> with type PAD ERROR:NgdBuild:924 - input pad net 'Add_Rnd/Correct_B<10>' is driving non-buffer primitives: pin I1 on block Add_Rnd/DigitSum/LUT4_inst with type LUT4, pin I1 on block Add_Rnd/DigitSum/LUT5_inst with type LUT5, pin O on block Add_Rnd/Correct_B<10>1 with type LUT5, pin I2 on block Add_Rnd/SelectS0OrS1<0>227 with type LUT6, pin I2 on block Add_Rnd/SelectS0OrS1<0>113_F with type LUT6, pin I3 on block Add_Rnd/SelectS0OrS1<0>113_G with type LUT6 Do i need to instantiated an additional component so that the tool can pipeline these LUT's ?!!!!!! I also implemented a smaller entity in the hierarchy in which i instantiate LUT's and this error did not appear .. then why this happened with the top design entity ?!!!! Am afraid this is a bug with the tool :( Am using ISE12.1 Thanks in advance :D 0
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答案对人有帮助，有参考价值 0 这很奇怪我注意到设计层次结构中的一个小组件没有被添加..像往常一样通过合成这是ISE的一个非常大的问题:(特别针对大型设计，仅合成时可能需要长达3小时的合成... 翻译过程发现一个单位是missign然后我添加这个实体并重新合成:( :(这太无聊和失去时间.. 在这种情况下，翻译甚至没有通知我这个缺失的组件..并且偶然我发现这个组件丢失..虽然你可以阅读错误信息，但没有给我任何指示我建议，如果缺少任何设计层次结构组件，ISE应该在合成过程中产生和出错，而不是等待几个小时的大型设计进行综合，并在转换阶段发现缺少组件并重复很长的合成过程 ..除非有smth。关于我还不知道的工具：D 阿姆鲁以上来自于谷歌翻译以下为原文 This is very strange I noticed that one of the small components of the design hierarchy was not added .. the synthesis as usual passed which is a very big problem with ISE :( specilally for large designs which can consume up to 3 hours for synthesis only .. after synthesis the translate process finds out that a unit is missign then i add this entity and re-synthesis :( :( this is too boring and loosing time .. In this case translate did not even inform me about this missing component .. and by chance i found out that this component is missing .. while you can read the error messages which did not give me any indication I suggest that ISE should produce and error while synthesis process if any of the design hierarchy components are missing instead of waiting several hours for large designs to synthesis and find out at the translate phase that there is a missing component and repeat a very long synthesis process .. unless there is smth. about the tool i do not know yet :D Amr

2018-10-10 11:02:36 评论举报费晨