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我有一个模块,我想在我的设计中使用它有一个DO NOT TOUCH属性的信号。当我试图生成比特流时,我收到了一个错误信号,因为它有组合循环。我使用了ALLOW_COMBINATORIAL_LOOPS TRUE
对带有错误的网络进行约束并再次生成比特流,但它不起作用。 它是否与属性有关?如何检查约束是否有效?我不想用属性触摸源代码,但如果这是唯一的解决方案,我会这样做。 以上来自于谷歌翻译 以下为原文 I have a module which I want to use in my design which has a signal with a DON'T TOUCH attribute. When I tried to generate the bitstream, I have received an error on this signal because it had combinatorial loops. I used the ALLOW_COMBINATORIAL_LOOPS TRUE constraint on the nets with the error and generated the bitstream again but it didn't work. Does it have something to do with the attribute? How can i check if a constraint is active? I prefer not to touch the source code with the attribute but I will if this is the only solution. |
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4个回答
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嗨,@ arthur42,请先参考以下链接:https://forums.xilinx.com/t5/Implementation/How-to-apply-set-property-ALLOW-COMBINATORIAL-LOOPS-TRUE-to-pass/mp
/ 781323#M18432 -------------------------------------------------- -----------------------不要忘记回答,kudo,并接受为解决方案.------------- -------------------------------------------------- ---------- 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi, @arthur42 , Please refer to the below link first: https://forums.xilinx.com/t5/Implementation/How-to-apply-set-property-ALLOW-COMBINATORIAL-LOOPS-TRUE-to-pass/m-p/781323#M18432 ------------------------------------------------------------------------- Don't forget to reply, kudo, and accept as solution. -------------------------------------------------------------------------View solution in original post |
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嗨,@ arthur42,请先参考以下链接:https://forums.xilinx.com/t5/Implementation/How-to-apply-set-property-ALLOW-COMBINATORIAL-LOOPS-TRUE-to-pass/mp
/ 781323#M18432 -------------------------------------------------- -----------------------不要忘记回答,kudo,并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Hi, @arthur42 , Please refer to the below link first: https://forums.xilinx.com/t5/Implementation/How-to-apply-set-property-ALLOW-COMBINATORIAL-LOOPS-TRUE-to-pass/m-p/781323#M18432 ------------------------------------------------------------------------- Don't forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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@ arthur42,
您是否实际检查了原理图并在组合循环上进行验证? 问题主要是由于RTL代码不正确。 请查看以下论坛链接: https://forums.xilinx.com/t5/Synthesis/Debugging-combinatorial-loop/td-p/684698 https://forums.xilinx.com/t5/Implementation/DRC-LUTLP-1-Combinatorial-Loop-Error-bitstream-generation-failed/td-p/833650 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @arthur42, Did you actually check the schematic and validate on the combinational loop? The issue is mostly due to incorrect RTL code. Please check the following forums link: https://forums.xilinx.com/t5/Synthesis/Debugging-combinatorial-loop/td-p/684698 https://forums.xilinx.com/t5/Implementation/DRC-LUTLP-1-Combinatorial-Loop-Error-bitstream-generation-failed/td-p/833650 --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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