是否可以为综合和实施流程保留不同的约束文件？

@ dmitry1417，
是的，您应该看到相同的时钟组用于综合和
实现。
你能检查一下从合成设计中修剪掉的时钟的连接性吗？
您可以使用两个不同的xdc文件，并为单个xdc文件设置“Used In”属性，如下所示：
请查看以下用户指南中的第83页：
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug895-vivado-system-level-design-entry.pdf#nameddest=xWorkingWithConstraints
如果时钟被修整，则对实现xdc文件应用相同的时钟组约束将发出警告，指出异步时钟组中的指定时钟丢失。
--Syed
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以下为原文

@dmitry1417,
 
Yes, You should see the same clock groups for both synthesis & implementation. 
Can you check the connectivity of the clock which got trimmed from synthesized design? 
 
You can  have two different xdc files and set "Used In" properties for the individual xdc file as shown below:

 
Check out page number 83 in the below User guide:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug895-vivado-system-level-design-entry.pdf#nameddest=xWorkingWithConstraints
 
If the clock is trimmed then applying the same clock group constraint for the implementation xdc file will give a warning that the specified clock in asynchronous clock groups is missing.
 
--Syed
 
 
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@ dmitry1417，
共享信息是否已回答您的查询？
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@dmitry1417,
 
Did the shared information answered your query?
 
--Syed
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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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