ISE 14.7 PAR路由与GLOBAL_LOGIC1冲突

你好@ nicosilicom
BRAM磁贴中的两个RAMB18站点共享ADDRATIEHIGH1 ADDRBTIEHIGH1资源。
当我们在这两个站点放置两个BRAM 18时，我们需要确保这些引脚上的信号是相同的。
在这种情况下，两个引脚具有不同的信号，因此路由器失败。
尝试将冲突的BRAM锁定到另一个不同的BRAM站点，看看它是否有帮助。
您可以在FPGA编辑器中打开部分路由设计，以查找当前位于RAMB18_x3Y64站点的BRAM实例。
如果您需要帮助，请在此处附上.ncd和.pcf文件。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）
在原帖中查看解决方案



以下为原文

Hi @nicosilicom
 
The Two RAMB18s sites in a BRAM tile share ADDRATIEHIGH1 ADDRBTIEHIGH1 resources. When we place two BRAM 18s in these two sites, we need to ensure that the signal on these pins are the same. In this case, the two pins have different signal, because of which the router fails.

Try locking one of the conflicting BRAMs to a different BRAM site and see if it helps.
 
You can open the partially routed design in FPGA editor to find the BRAM instance which is currently sitting in site RAMB18_x3Y64.
 
If you need help in doing this please attach .ncd and .pcf files here.
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)View solution in original post

你好@ nicosilicom
BRAM磁贴中的两个RAMB18站点共享ADDRATIEHIGH1 ADDRBTIEHIGH1资源。
当我们在这两个站点放置两个BRAM 18时，我们需要确保这些引脚上的信号是相同的。
在这种情况下，两个引脚具有不同的信号，因此路由器失败。
尝试将冲突的BRAM锁定到另一个不同的BRAM站点，看看它是否有帮助。
您可以在FPGA编辑器中打开部分路由设计，以查找当前位于RAMB18_x3Y64站点的BRAM实例。
如果您需要帮助，请在此处附上.ncd和.pcf文件。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi @nicosilicom
 
The Two RAMB18s sites in a BRAM tile share ADDRATIEHIGH1 ADDRBTIEHIGH1 resources. When we place two BRAM 18s in these two sites, we need to ensure that the signal on these pins are the same. In this case, the two pins have different signal, because of which the router fails.

Try locking one of the conflicting BRAMs to a different BRAM site and see if it helps.
 
You can open the partially routed design in FPGA editor to find the BRAM instance which is currently sitting in site RAMB18_x3Y64.
 
If you need help in doing this please attach .ncd and .pcf files here.
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

你好@ vemulad
感谢您的指示，我在另一篇文章（路由冲突）上找到了使用BLKNM约束的建议。
实际上，通过在所涉及的BRAM之一上使用XBLKNM约束，问题得以解决。
然而，两个不同的信号应该是相同的，因为信号“cfg_err_cor_int_n”等于'1'。
那么，为什么这个工具看不到呢？
问候，
萨科



以下为原文

Hi @vemulad
 
 
Thanks to your indications, I found the suggestion on another post (routing conflict) to use BLKNM constraint. In fact, by using the XBLKNM constraint on one of the BRAM involved, the problem is solved.
 
However, the two different signals should be the same because the signal "cfg_err_cor_int_n" is equal to '1'. So, why the tool does not see that?
 
 
Regards,
 
Nicolas
 

您好@nicosilicom您最终如何解决问题？
我最近也发生了同样的错误，我也不知道！你能给我一些建议吗，我很感激！
罗文



以下为原文

Hi @nicosilicom
   How do you slove the problem finally? The same errors have occured to me recently,and I have no idea for it!Can you give me some suggestions,I would appreciate it!

Rowen

你好@ lqvshq
我找到的唯一解决方案是通过添加或更改MAP或PAR指令，UCF约束或简单地使用新功能来指示工具进行另一个放置和路由...
我不明白为什么会这样。
萨科



以下为原文

Hi @lqvshq
 
The only solution I found is to direct the tool to make another placement and routing by adding or changing MAP or PAR directives, with UCF constraints, or simply with new functionalities...
 
I have not understand why this happens.
 
Nicolas

你好@ nicosilicom 
非常感谢你的回复。我的错误是由于oddr2，iddr2和iobuf的组合造成的，以便在Spartan-6中作为一个输入端口发挥作用。它直到Place＆amp;
XST在ISE 14.5之后的路线。上面的三个原语在斯巴达-6中不能很好地工作，是吗？
我如何处理iobuf中的T端口oftri-state。如果它被奇怪的驱动？
罗文



以下为原文

Hi @nicosilicom
  Thank you for your reply very much.The error of mine have caused by the combination of oddr2,iddr2 and iobuf  in order to function as a inout port in Spartan-6.It doesn't go on until the process of Place & Route after XST in the ISE 14.5.The three primitives of above can't work well in spartan-6,is it? How can I deal with the T port of tri-state gate in the iobuf.Should it be drived by oddr?
 
Rowen

你好@ lqvshq
我想我们需要更多细节来帮助你（错误，工具报告，代码......）但你应该能够通过将IOBUF的I（输入）引脚连接到ODDR2和O（输出）来使用ODDR2，IDDR2和IOBUFprimitives
）引脚到IDDR2。
如果要将三态引脚重定向到器件焊盘或驱动多个IOBUF，请注意三态引脚。
您是否看过“ug381  -  Spartan-6 FPGA Selectio Resources”？
萨科



以下为原文

Hi @lqvshq
 
I think we will need more details to help you (error, report of the tool, code ...) but you should be able to use ODDR2, IDDR2 and IOBUF primitives by connecting I (Input) pin of IOBUF to ODDR2 and O (Output) pin to IDDR2.
 
Take care about the tri-state pin if you are redirecting it to a device pad or driving multiple IOBUF.
 
Did you take a look at "ug381 - Spartan-6 FPGA Selectio Resources"?
 
Nicolas

None


以下为原文

Hi @nicosilicom
The error is:
   ERROR:Route:472 - This design is unrouteable.To evaluate the problem please use fpga_editor.
Details: 
ERROR:Route:472 -
This design is unrouteable.
To evaluate the problem please use fpga_editor.
Routing Conflict 1:
Net:w_clk_100m_180 on pin CLK1 on location OLOGIC_X0Y68
Net:w_clk_100m_270 on pin CLK1 on location ILOGIC_X0Y68
Conflict detected on wire: PINFEED1(-105576,-86958)
Routing Conflict 2:
Net:w_clk_100m_180 on pin CLK1 on location OLOGIC_X0Y70
Net:w_clk_100m_270 on pin CLK1 on location ILOGIC_X0Y70
Conflict detected on wire: PINFEED1(-105576,-76286)
Routing Conflict 3:
Net:w_clk_100m_180 on pin CLK1 on location OLOGIC_X0Y72
Net:w_clk_100m_270 on pin CLK1 on location ILOGIC_X0Y72
Conflict detected on wire: PINFEED1(-105576,-66686)
Routing Conflict 4:
Net:w_clk_100m_180 on pin CLK1 on location OLOGIC_X0Y74
Net:w_clk_100m_270 on pin CLK1 on location ILOGIC_X0Y74
Conflict detected on wire: PINFEED1(-105576,-57086)
Routing Conflict 5:
Net:w_clk_100m_180 on pin CLK1 on location OLOGIC_X0Y69
Net:w_clk_100m_270 on pin CLK1 on location ILOGIC_X0Y69
Conflict detected on wire: PINFEED1(-105566,-86926)
Routing Conflict 6:
Net:w_clk_100m_180 on pin CLK1 on location OLOGIC_X0Y71
Net:w_clk_100m_270 on pin CLK1 on location ILOGIC_X0Y71
Conflict detected on wire: PINFEED1(-105566,-76254)
Routing Conflict 7:
Net:w_clk_100m_180 on pin CLK1 on location OLOGIC_X0Y73
Net:w_clk_100m_270 on pin CLK1 on location ILOGIC_X0Y73
Conflict detected on wire: PINFEED1(-105566,-66654)
Routing Conflict 8:
Net:w_clk_100m_180 on pin CLK1 on location OLOGIC_X0Y75
Net:w_clk_100m_270 on pin CLK1 on location ILOGIC_X0Y75
Conflict detected on wire: PINFEED1(-105566,-57054)
Total REAL time to Router completion: 5 secs
Total CPU time to Router completion: 4 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| w_clk_16p5m* | BUFGMUX_X2Y12| No | 64 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| w_clk_100m_270* | BUFGMUX_X2Y2| No | 14 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| w_clk_100m* | BUFGMUX_X2Y1| No | 200 icon_CONTROL0<0>* | BUFGMUX_X2Y10| No | 87 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| w_clk_100m_90* | BUFGMUX_X3Y13| No | 12 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
|u_icon/U0/iUPDATE_OU | | | | | |
| T* | Local| | 1 | 0.000 | |
+---------------------+--------------+------+------+------------+-------------+
| w_clk_100m_180* | BUFGMUX_X2Y4| No | 9 | | |
+---------------------+--------------+------+------+------------+-------------+
* Some of the Clock networks are NOT completely routed
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
| icon_CONTROL1<13>* | Local| | 5 | 0.000Timing Score: 650781 (Setup: 650781, Hold: 0, Component Switching Limit: 0)
 
Code:
ODDR2 #(.DDR_ALIGNMENT("C1"),
.INIT(1'b0),
.SRTYPE("ASYNC")
) ODDR2_dq_out_en0
(.Q(w_dq_out_en0),
.C0(i_clk),
.C1(i_clk_180),
.CE(1'b1),
.D0(w_dq_out_en_tmp),
.D1(w_dq_out_en_tmp),
.R(1'b0),
.S(1'b0));
 
The oddr2 is to drive the T pin of tri-state gate,and I am not sure the reasonability of it.
 
io_ddr_m u_dq0(
.i_clko(i_clk),
.i_clko_180(i_clk_180),
.i_clki(i_clk_90),
.i_clki_180(i_clk_270),
.i_wr_en(r_dq_vaild),
.i_rd_en(r_data_flag),
.i_outen(w_dq_out_en0),
.i_oddr_rst(1'b0),
.i_oddr_st(1'b0),
.i_iddr_rst(1'b0),
.i_iddr_st(1'b0),
.i_d0(r_dq1[0]),
.i_d1(r_dq2[0]),
.io_dq(io_DQ[0]),
.o_di_0(w_data1[0]),
.o_di_1(w_data2[0])
);
 
The module is to function as a bidirectional pin named io_DQ,it has eight bit width.So there are eight modules in total.The net called w_dq_out_en0 is T pin.

module io_ddr_m (
input i_clko
,input i_clko_180
,input i_clki
,input i_clki_180
,input i_wr_en
,input i_rd_en
,input i_outen
,input i_oddr_rst
,input i_oddr_st
,input i_iddr_rst
,input i_iddr_st

,input i_d0
,input i_d1

,inout io_dq

,output o_di_0
,output o_di_1
);

wire w_oddr_q;
wire w_iobuf_q;

ODDR2 #(
.DDR_ALIGNMENT("C1"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst (
.Q(w_oddr_q), // 1-bit DDR output data
.C0(i_clko), // 1-bit clock input
.C1(i_clko_180), // 1-bit clock input
.CE(i_wr_en), // 1-bit clock enable input
.D0(i_d0), // 1-bit data input (associated with C0)
.D1(i_d1), // 1-bit data input (associated with C1)
.R(i_oddr_rst), // 1-bit reset input
.S(i_oddr_st) // 1-bit set input
);

IDDR2 #(
.DDR_ALIGNMENT("C1"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) IDDR2_inst0 (
.Q0(o_di_0), // 1-bit output captured with C0 clock
.Q1(o_di_1), // 1-bit output captured with C1 clock
.C0(i_clki), // 1-bit clock input
.C1(i_clki_180), // 1-bit clock input
.CE(i_rd_en), // 1-bit clock enable input
.D(w_iobuf_q), // 1-bit DDR data input
.R(i_iddr_rst), // 1-bit reset input
.S(i_iddr_st) // 1-bit set input
);

IOBUF #(
.DRIVE(12), // Specify the output drive strength
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
.O(w_iobuf_q), // Buffer output
.IO(io_dq), // Buffer inout port (connect directly to top-level port)
.I(w_oddr_q), // Buffer input
.T(i_outen) // 3-state enable input, high=input, low=output
);
/*********************************************************/

endmodule