请问DRC RTSTAT-1与FIFO生成器的部分冲突应该如何解决？

你好@ pgrangeray
这是vivado 2017.2中的一个已知问题。
这将在2017年修复。
查看此主题以获取更多详细信息：//forums.xilinx.com/t5/Inmplementation/VIVADO-2017-1-ERROR-DRC-RTSTAT-6-Partial-route-conflicts-2-net-s/td-p/762078
由于FIFO位于加密IP内，因此您需要使用ECO命令将REGCE引脚连接到Vcc。
可以在上面的线程中找到示例约束集。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
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在原帖中查看解决方案



以下为原文

Hi @pgrangeray
 
This is a known issue in vivado 2017.2. This will be fixed in 2017.3. Check this thread for more details https://forums.xilinx.com/t5/Implementation/VIVADO-2017-1-ERROR-DRC-RTSTAT-6-Partial-route-conflicts-2-net-s/td-p/762078
 
As the FIFO is inside the encrypted IP, you need to ECO commands to connect the REGCE pins to Vcc instead. Example set of constraints can be found in above thread.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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和MIG 7系列的警告：
[DRC RTSTAT-10]无可路由负载：2063网络没有可路由负载。
问题总线（ES）和/或净（S）是memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_0.u_ddr_phy_4lanes / ddr_byte_lane_A.ddr_byte_lane_A / A_pi_dqs_out_of_range，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 /
ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_0.u_ddr_phy_4lanes / ddr_byte_lane_A.ddr_byte_lane_A / A_pi_fine_overflow，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_1.u_ddr_phy_4lanes / A_pi_rst_div2，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 /
u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_0.u_ddr_phy_4lanes / A_pi_rst_div2，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_0.u_ddr_phy_4lanes /
ddr_byte_lane_A.ddr_byte_lane_A / A_po_coarse_overflow，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_0.u_ddr_phy_4lanes / ddr_byte_lane_A.ddr_byte_lane_A / A_po_fine_overflow，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_0。
u_ddr_phy_4lanes / ddr_byte_lane_B.ddr_byte_lane_B / B_of_a_full，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_1.u_ddr_phy_4lanes / B_pi_rst_div2，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_0.u_ddr_phy_4lanes /
B_pi_rst_div2，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_0.u_ddr_phy_4
泳道/ ddr_byte_lane_B.ddr_byte_lane_B / B_po_coarse_overflow，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_0.u_ddr_phy_4lanes / ddr_byte_lane_B.ddr_byte_lane_B / B_po_fine_overflow，象形字/ counter_addr / U0 / i_synth / i_baseblox.i_baseblox_counter / the_addsub / no_pipelining。
the_addsub / i_lut6.i_lut6_addsub / CI，pixel_index_0 / counter_0 / U0 / i_synth / i_baseblox.i_baseblox_counter / the_addsub / no_pipelining.the_addsub / i_lut6.i_lut6_addsub / CI，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_0。
u_ddr_phy_4lanes / ddr_byte_lane_C.ddr_byte_lane_C / C_of_a_full，memory_controler_1 / u_mig_7series_0 / u_mig_7series_0_mig / u_memc_ui_top_std / mem_intfc0 / ddr_phy_top0 / u_ddr_mc_phy_wrapper / u_ddr_mc_phy / ddr_phy_4lanes_1.u_ddr_phy_4lanes / C_pi_rst_div2 ...和（1857年的前15中列出）。
如何获得整个列表？



以下为原文

And warning on MIG 7 series :
 
[DRC RTSTAT-10] No routable loads: 2063 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/A_pi_dqs_out_of_range, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/A_pi_fine_overflow, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_rst_div2, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_rst_div2, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/A_po_coarse_overflow, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/A_po_fine_overflow, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/B_of_a_full, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/B_pi_rst_div2, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_rst_div2, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/B_po_coarse_overflow, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/B_po_fine_overflow, picto/counter_addr/U0/i_synth/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/CI, pixel_index_0/counter_0/U0/i_synth/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/CI, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/C_of_a_full, memory_controler_1/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_pi_rst_div2... and (the first 15 of 1857 listed).
 
How to get the entire list?

你好@ pgrangeray
这是vivado 2017.2中的一个已知问题。
这将在2017年修复。
查看此主题以获取更多详细信息：//forums.xilinx.com/t5/Inmplementation/VIVADO-2017-1-ERROR-DRC-RTSTAT-6-Partial-route-conflicts-2-net-s/td-p/762078
由于FIFO位于加密IP内，因此您需要使用ECO命令将REGCE引脚连接到Vcc。
可以在上面的线程中找到示例约束集。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi @pgrangeray
 
This is a known issue in vivado 2017.2. This will be fixed in 2017.3. Check this thread for more details https://forums.xilinx.com/t5/Implementation/VIVADO-2017-1-ERROR-DRC-RTSTAT-6-Partial-route-conflicts-2-net-s/td-p/762078
 
As the FIFO is inside the encrypted IP, you need to ECO commands to connect the REGCE pins to Vcc instead. Example set of constraints can be found in above thread.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

嗨@ vemulad @ hpoetzl
谢谢你的回复。
我读了这个关于已知问题的话题，但我还没有真正理解你的答案......
现在我明白了，问题解决了！
比特流生成完成了！
只是一些与tcl.pre相关的警告:(其中很少）
[Vivado 12-508]没有引脚匹配'system_i / inst_ignis_zynq_udp_intf / inst / inst_builtin_bram_fifo_rx / no_cascade_by_depth.inst_builtin_bram_fifo_base / use_fifo18e1_inst.fifo18e1_inst [0] .inst_fifo18e1 / REGCE'。
[Vivado 12-508]没有引脚匹配'system_i / inst_arches_udp_ip / inst / inst_arches_udp_ip_stack / inst_arches_udp_ip_rx / inst_meas_oled_data_fifo / no_cascade_by_depth.inst_builtin_bram_fifo_base / use_fifo18e1_inst.fifo18e1_inst [0] .inst_fifo18e1 / REGCE'。
[Coretcl 2-30]找不到net'system_i / inst_arches_udp_ip / inst / inst_arches_udp_ip_stack / inst_arches_udp_ip_rx / inst_meas_oled_data_fifo / no_cascade_by_depth.inst_builtin_bram_fifo_base /'。
[Coretcl 2-30]找不到net'system_i / inst_arches_udp_ip / inst / inst_axis_width_conv_dr_fifo / include_wc.upsizing.use_cdc_fifo.inst_axis_builtin_bram_fifo / inst_builtin_bram_fifo / no_cascade_by_depth.inst_builtin_bram_fifo_base /'。
有可能解决它，或者我可以忽略它？
谢谢！



以下为原文

Hi @vemulad @hpoetzl
 
Thank you for your responses.
I read this topic about known issue but I haven't realy understood your answer...
 
Now i understand and problem solved! 
Bitstream generation is done!
 
Just some warning related to the tcl.pre : (few of them) 
 
[Vivado 12-508] No pins matched 'system_i/inst_ignis_zynq_udp_intf/inst/inst_builtin_bram_fifo_rx/no_cascade_by_depth.inst_builtin_bram_fifo_base/use_fifo18e1_inst.fifo18e1_inst[0].inst_fifo18e1/REGCE'.
 
[Vivado 12-508] No pins matched 'system_i/inst_arches_udp_ip/inst/inst_arches_udp_ip_stack/inst_arches_udp_ip_rx/inst_meas_oled_data_fifo/no_cascade_by_depth.inst_builtin_bram_fifo_base/use_fifo18e1_inst.fifo18e1_inst[0].inst_fifo18e1/REGCE'.
 
[Coretcl 2-30] Cannot find net 'system_i/inst_arches_udp_ip/inst/inst_arches_udp_ip_stack/inst_arches_udp_ip_rx/inst_meas_oled_data_fifo/no_cascade_by_depth.inst_builtin_bram_fifo_base/'.
 
[Coretcl 2-30] Cannot find net 'system_i/inst_arches_udp_ip/inst/inst_axis_width_conv_dr_fifo/include_wc.upsizing.use_cdc_fifo.inst_axis_builtin_bram_fifo/inst_builtin_bram_fifo/no_cascade_by_depth.inst_builtin_bram_fifo_base/'.
 
Is it possible to solve it, or i can ignore?
 
Thanks!

你好@ pgrangeray
您需要根据您的设计更改命令中的网络名称。
你能共享位于.runs / impl_1文件夹中的_placed.dcp吗？
我可以帮助你正确的命令。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
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以下为原文

Hi @pgrangeray
 
You need to change the net names in the command according to your design.
 
Can you share the _placed.dcp located in .runs/impl_1 folder? I can help you with correct commands.
 
 
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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@vemulad
附上文件。
谢谢你的帮助。
top_placed.dcp 3949 KB



以下为原文

@vemulad
 
Attached the file.
 
Thank you for your aid.
            top_placed.dcp ‏3949 KB

你好@ pgrangeray
在此DCP Idont中看到DRC错误，route_design成功完成。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi @pgrangeray
 
In this DCP I dont see the DRC error, route_design completes successfully. 
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

@vemulad
没有错误，只有警告！
也许，我可以找到好名字。
告诉我你如何找到正确的名称等。



以下为原文

@vemulad
 
No error, only warnings!
 
Maybe, i can find good names. Tell me how do you find correct names for etc..

你好@ pgrangeray
您可以使用“编辑” - >“查找”选项打开已实现的设计并查找这些网络。
以下是您在第一篇文章中提到的有问题FIFO的层次结构中的网络
FIFO_MCU_0 / U0 / inst_fifo_gen / gconvfifo.rf / gbi.bi / v7_bi_fifo.fblk / gextw [1] .gnll_fifo.inst_extd / gonep.inst_prim /
const1处于不同的层次结构中，因此您需要使用connect_net命令的-hier开关
FIFO_MCU_0 / U0 / inst_fifo_gen / gconvfifo.rf / gbi.bi / v7_bi_fifo.fblk /
FIFO引脚名称
FIFO_MCU_0 / U0 / inst_fifo_gen / gconvfifo.rf / gbi.bi / v7_bi_fifo.fblk / gextw [1] .gnll_fifo.inst_extd / gonep.inst_prim / gf36e1_inst.sngfifo36e1 / REGCE
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi @pgrangeray
 
You can open implemented design and look for these nets using Edit --> Find option.
 
Below is the net in the hiearchy of problematic FIFO mentioned in your first post
 
FIFO_MCU_0/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/
 
const1 is in a different hierarchy so you need to use -hier switch of connect_net command
 
FIFO_MCU_0/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/
 
FIFO pin name
 
FIFO_MCU_0/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/REGCE
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)