write_bitstream日志出现错误

喜@ VOCO  - 曼海姆
这看起来像一个错误，你可以共享路由检查点供我们调试吗？
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi @voco-mannheim
 
This looks like a bug, can you share the post route checkpoint for us to debug?
Thanks,
Deepika.
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嗨Deepika，
感谢您的回复。
随附的是路线后检查站。
是否有临时解决方法来避免此问题？
谢谢。
hmc_test_top_routed.dcp 5490 KB



以下为原文

Hi Deepika,
 
thank's for your reply. Attached is the post route checkpoint.
 
Is there a temporary workaround to avoid this issue?
 
 
Thanks.
            hmc_test_top_routed.dcp ‏5490 KB

喜@ VOCO  - 曼海姆
由于共享连接，LAGUNA磁贴中的TX触发器BEL应具有相同的SRVAL和FFINIT属性。
在您的设计中，具有不同SRVAL和FFINIT属性的触发器被放置在相同的区块中，因此出现错误。
以下是LAGUNA_TILE_X51Y618 tile中具有SRHIGH和INIT1的触发器，此块中的其他触发器具有SRLOW和INIT0。
如果将这些触发器移动到切片或不同的LAGUNA站点，则不会出现此问题。
lan_modul_inst1 / LAN_IP_INST1 / LAN_SGMII_GMII_INST1 / sgmii_gmii_bridge_i / U0 / pcs_pma_block_i / lvds_transceiver_mw / serdes_1_to_10_ser8_i / bt_val_rawa_reg [6]
lan_modul_inst1 / LAN_IP_INST1 / LAN_SGMII_GMII_INST1 / sgmii_gmii_bridge_i / U0 / pcs_pma_block_i / lvds_transceiver_mw / serdes_1_to_10_ser8_i / bt_val_rawa_reg [4]
您可以在已实现的设计中取消放置和放置/路由这些触发器。
您可以在传递设计中检查这些触发器的位置，并在失败的设计中使用相同的触发器。
FYI ..我们工厂知道这个问题，并计划为此发出DRC错误。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi @voco-mannheim
 
The TX flop BELs in a LAGUNA tile should have same SRVAL and FFINIT properties due to shared connectivity. In your design flops with different SRVAL and FFINIT properties are placed in same tile hence the error.
 
Below are the flops in LAGUNA_TILE_X51Y618 tile which have SRHIGH and INIT1, other flops in this tile have SRLOW and INIT0. If these flops are moved to slice or to a different LAGUNA site then this issue will not be seen.
 
lan_modul_inst1/LAN_IP_INST1/LAN_SGMII_GMII_INST1/sgmii_gmii_bridge_i/U0/pcs_pma_block_i/lvds_transceiver_mw/serdes_1_to_10_ser8_i/bt_val_rawa_reg[6]
 
lan_modul_inst1/LAN_IP_INST1/LAN_SGMII_GMII_INST1/sgmii_gmii_bridge_i/U0/pcs_pma_block_i/lvds_transceiver_mw/serdes_1_to_10_ser8_i/bt_val_rawa_reg[4]
 
You can unplace and place/route these flops in implemented design. You can checkout the placement of these flops in passing design and use the same in failing design.
 
FYI..our factory is aware of this issue and is planning to issue an DRC error for this.
Thanks,
Deepika.
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喜@ VOCO  - 曼海姆
那帮了吗？
仅供参考。我已提交CR 961465以改进write_bitstream中的消息传递。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi @voco-mannheim
 
Did that help?
 
FYI..I had filed CR 961465 to improve the messaging in write_bitstream.
Thanks,
Deepika.
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