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大家好，当我尝试在本教程中生成比特流时：
http://blog.idv-tech.com/2014/05 ... linx-vivado-2014-1/ 由于以下错误，未生成比特流： 错误：[Drc 23-20]规则违规（NSTD-1）未指定的I / O标准 - 141个逻辑端口中的11个使用I / O标准（IOSTANDARD）值'DEFAULT'，而不是用户指定的特定值。 这可能导致I / O争用或与电路板电源或连接不兼容，从而影响性能，信号完整性或在极端情况下导致设备或其所连接的组件受损。 要更正此违规，请指定所有I / O标准。 除非所有逻辑端口都定义了用户指定的I / O标准值，否则此设计将无法生成比特流。 要允许使用未指定的I / O标准值创建比特流（不推荐），请使用以下命令：set_property SEVERITY {Warning} [get_drc_checks NSTD-1]。 注意：使用Vivado运行基础结构（例如，launch_runs Tcl命令）时，将此命令添加到.tcl文件，并将该文件添加为执行运行的write_bitstream步骤的预挂钩。 问题端口：SPI0_CS [7：0]，SPI0_MISO，SPI0_MOSI，SPI0_SCLK。 错误：[Drc 23-20]规则违规（UCIO-1）无约束逻辑端口 - 141个逻辑端口中的4个没有用户分配特定位置约束（LOC）。 这可能导致I / O争用或与电路板电源或连接不兼容，从而影响性能，信号完整性或在极端情况下导致设备或其所连接的组件受损。 要更正此违规，请指定所有引脚位置。 除非所有逻辑端口都定义了用户指定的站点LOC约束，否则此设计将无法生成比特流。 要允许使用未指定的引脚位置创建比特流（不推荐），请使用以下命令：set_property SEVERITY {Warning} [get_drc_checks UCIO-1]。 注意：使用Vivado运行基础结构（例如，launch_runs Tcl命令）时，将此命令添加到.tcl文件，并将该文件添加为执行运行的write_bitstream步骤的预挂钩。 问题端口：SPI0_CS [7]，SPI0_CS [6]，SPI0_CS [5]，SPI0_CS [4] .ERROR：[Vivado 12-1345]在DRC期间发现错误。 比特根没跑。 本教程有一些错误，例如拼错的模块名称（包含像“ - ”这样的禁用字符串）和图中拼写错误的IO端口名称，xdc文件是否正确？ 另外，我有一些严重警告，如： [Board 49-4]解析board_part文件时出现问题 - C：/Xilinx/Vivado/2014.2/data/boards/board_parts/kintex7/kc705/0.9/board_part.xml，电路板部分'xc7k325tffg900-2'不受支持或无效 。 这是正常的吗？ 感谢您的答复 以上来自于谷歌翻译 以下为原文 Hi all, when i try to generate the bitstream in this tutorial: http://blog.idv-tech.com/2014/05 ... linx-vivado-2014-1/ The bitstream is not generated due to the following error: ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 11 out of 141 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: SPI0_CS[7:0], SPI0_MISO, SPI0_MOSI, SPI0_SCLK. ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 4 out of 141 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: SPI0_CS[7], SPI0_CS[6], SPI0_CS[5], SPI0_CS[4]. ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. The tutorial has some error, for example the mispelled module name (containing forbidden charachter like "-") and the mispelled IO Port name in the figure, is the xdc file correct? Additionally i have some critical warning like: [Board 49-4] Problem parsing board_part file - C:/Xilinx/Vivado/2014.2/data/boards/board_parts/kintex7/kc705/0.9/board_part.xml, The board part 'xc7k325tffg900-2' is either not supported or invalid. Is this normal? Thank you for the reply 
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5个回答
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嗨，
该错误是因为尚未将LOC和IOSTANDARD分配给所有顶级端口。 您是否为XDC中的错误中提到的端口编写了LOC和IOSTANDARD约束？ 你能附上位于.runs - > impl_1位置的runme.log文件吗？ 相关ARhttp：//www.xilinx.com/support/answers/56354.html 谢谢， 迪皮卡。 谢谢，迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星） 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi, The error is because the LOC and IOSTANDARD has not been assigned to all of the top level ports. Did you write LOC and IOSTANDARD constraints for the ports mentioned in the error in your XDC? Can you attach runme.log file located in .runs --> impl_1 location? Related AR http://www.xilinx.com/support/answers/56354.html Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)View solution in original post |
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您好，请查看以下ARhttp：//www.xilinx.com/support/answers/56354.html
问候，阿希什----------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - -请注意- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。感谢Kudos .-------------------- -------------------------------------------------- ------------------------ 以上来自于谷歌翻译 以下为原文 Hello, Please check below AR http://www.xilinx.com/support/answers/56354.htmlRegards, Ashish ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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嗨，
该错误是因为尚未将LOC和IOSTANDARD分配给所有顶级端口。 您是否为XDC中的错误中提到的端口编写了LOC和IOSTANDARD约束？ 你能附上位于.runs - > impl_1位置的runme.log文件吗？ 相关ARhttp：//www.xilinx.com/support/answers/56354.html 谢谢， 迪皮卡。 谢谢，迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星） 以上来自于谷歌翻译 以下为原文 Hi, The error is because the LOC and IOSTANDARD has not been assigned to all of the top level ports. Did you write LOC and IOSTANDARD constraints for the ports mentioned in the error in your XDC? Can you attach runme.log file located in .runs --> impl_1 location? Related AR http://www.xilinx.com/support/answers/56354.html Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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你在这里，现在我注意到SPI0_CS端口的xdc文件中的约束是4，但模块的输出是8位宽，这可能是错误吗？
runme.log 27 KB 以上来自于谷歌翻译 以下为原文 here you are, now i have noticed that the constraints in the xdc file for the SPI0_CS port are 4, but the output of the module is 8 bits wide, can be this the error? |
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我添加了未连接的端口并成功生成了比特流，谢谢！
以上来自于谷歌翻译 以下为原文 i have added the unconnected port and the bitstream was generated successfully, thank you! |
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