用户具有过度约束的组件ioclk_buf

我在使用我的斯巴达6xc6slx45-3csg324 FPGA进行映射时出现以下错误。
“错误：位置：1318： - 用户具有过度约束的组件ioclk_buf。没有可放置的站点满足用户约束。请查看驱动程序组件的用户约束和ioclk_buf的加载组件。
错误：打包：1654： - 时序驱动的放置阶段遇到错误。“
ioclk_buf是BUFPLL原语的对象，我用它来生成高速IO时钟（主时钟的一半）。
下面是我的设计的ucf文件，我想在我的Atlys主板上使用HDMI端口同时在两个屏幕上显示彩条。
我的设计的顶级模块也附加。
我对这个问题的看法是由于bufpll（ioclk_buf）的不正确的布局规划。
############################################为不同的SP601板设置VCCAUX
############################################ VCCAUX = 3.3;
#########################################重置按钮和LED #####
################################### NET“RSTBTN”LOC =“N4”; NET“LED”LOC
=“H12”; NET“LED”LOC =“G13”; NET“LED”LOC =“E16”; NET“LED”LOC =“E18”;
##################################################
############################# SYSCLK输入###################
##################################################
######### NET“SYS_CLK”LOC =“L15”;
##################################################
#############################机械开关（SW）################
##################################################
############ NET“SW”LOC =“A10”| IOSTANDARD = LVCMOS33; NET“SW”LOC =“D14”| IOSTANDARD = LVCMOS33; NET“SW”LOC =“C14”|
IOSTANDARD = LVCMOS33; NET“SW”LOC =“P15”| IOSTANDARD = LVCMOS33;
##################################################
#############################调试端口＃JA1 #################
##################################################
########### NET“DEBUG [0]”LOC =“B12”| IOSTANDARD = LVCMOS33; NET“DEBUG [1]”LOC =“B11”| IOSTANDARD = LVCMOS33;
##################################################
############################# DCM / PLL / BUFPLL职位###############
##################################################
############## INST“PCLK_GEN_INST”LOC =“DCM_X0Y3”;
#INST “PLL_OSERDES” LOC = “PLL_ADV_X0Y1”;＃INST “ioclk_buf” LOC = “BUFPLL_X1Y0”; ############################
################时间约束################################
########### NET “clk50m_bufg” TNM_NET = “TNM_CLK50M”; tiMESPEC “TS_CLK50M”= PERIOD “TNM_CLK50M” 50兆赫HIGH 50％优先级0;
NET“pclk”TNM_NET =“TNM_PCLK”; TIMESPEC“TS_PCLK”= PERIOD“TNM_PCLK”108 MHz HIGH 50％PRIORITY 0;
NET“pclkx2”TNM_NET =“TNM_PCLKX2”; TIMESPEC“TS_PCLKX2”= PERIOD“TNM_PCLKX2”TS_PCLK * 2;
NET“pclkx10”TNM_NET =“TNM_PCLKX10”; TIMESPEC“TS_PCLKX10”= PERIOD“TNM_PCLKX10”TS_PCLK * 10;
##多循环路径#TIMEGRP“bramgrp”= RAMS（enc0 / pixel2x / dataint）;
TIMEGRP“fddbgrp”= FFS（enc0 / pixel2x / db）; TIMEGRP“bramra”= FFS（enc0 / pixel2x / ra）;
TIMEGRP“bramgrp”= RAMS（enc1 / pixel2x / dataint）;
TIMEGRP“fddbgrp”= FFS（enc1 / pixel2x / db）; TIMEGRP“bramra”= FFS（enc1 / pixel2x / ra）;
TIMESPEC“TS_ramdo”=从“bramgrp”到“fddbgrp”TS_PCLK; TIMESPEC“TS_ramra”=从“bramra”到“fddbgrp”TS_PCLK;
顶部###########################
############ NET“TMDS2（0）”LOC =“R3”| IOSTANDARD = TMDS_33;
#BlueNET“TMDSB2（0）”LOC =“T3”| IOSTANDARD = TMDS_33; NET“TMDS2（1）”LOC =“T4”| IOSTANDARD = TMDS_33;
#RedNET“TMDSB2（1）”LOC =“V4”| IOSTANDARD = TMDS_33; NET“TMDS2（2）”LOC =“N5”| IOSTANDARD = TMDS_33;
#GreenNET“TMDSB2（2）”LOC =“P6”| IOSTANDARD = TMDS_33; NET“TMDS2（3）”LOC =“T9”| IOSTANDARD = TMDS_33;
＃ClockNET“TMDSB2（3）”LOC =“V9”| IOSTANDARD = TMDS_33;
NET“TMDS1（0）”LOC =“D8”| IOSTANDARD = TMDS_33;
#BlueNET“TMDSB1（0）”LOC =“C8”| IOSTANDARD = TMDS_33; NET“TMDS1（1）”LOC =“C7”| IOSTANDARD = TMDS_33;
#RedNET“TMDSB1（1）”LOC =“A7”| IOSTANDARD = TMDS_33; NET“TMDS1（2）”LOC =“B8”| IOSTANDARD = TMDS_33;
#GreenNET“TMDSB1（2）”LOC =“A8”| IOSTANDARD = TMDS_33; NET“TMDS1（3）”LOC =“B6”| IOSTANDARD = TMDS_33;
＃ClockNET“TMDSB1（3）”LOC =“A6”| IOSTANDARD = TMDS_33;
请帮我解决这个问题。
谢谢
vtc_demo.v 21 KB



以下为原文

I am getting the following error on mapping with my spartan 6 xc6slx45-3csg324 fpga.

"ERROR:Place:1318: - User has over-constrained component ioclk_buf. There are no placeable sites that satisfy the user constraints. Please review the user constraints on the driver component and the load components of ioclk_buf.

ERROR:Pack:1654: - The timing-driven placement phase encountered an error."

ioclk_buf is an object of BUFPLL primitive that is used by me for generating high speed IO clock (half of the main clock).
Below is the ucf file of my design in which I want to display color bars on two screens simultaneously using HDMI ports on my Atlys board. Top level module of my design is also attached. What I think about this issue is that is due to incorrent floorplanning of bufpll (ioclk_buf).

###########################################
# Setting VCCAUX for different SP601 board
###########################################
VCCAUX = 3.3;
########################################
# Reset button and LEDs
########################################
NET "RSTBTN" LOC = "N4";
NET "LED<0>" LOC = "H12";
NET "LED<1>" LOC = "G13";
NET "LED<2>" LOC = "E16";
NET "LED<3>" LOC = "E18";
##############################################################################
# SYSCLK Input
##############################################################################
NET "SYS_CLK" LOC = "L15";
##############################################################################
# Mechanical Switches (SW)
##############################################################################
NET "SW<0>" LOC = "A10" |IOSTANDARD = LVCMOS33 ;
NET "SW<1>" LOC = "D14" |IOSTANDARD = LVCMOS33 ;
NET "SW<2>" LOC = "C14" |IOSTANDARD = LVCMOS33 ;
NET "SW<3>" LOC = "P15" |IOSTANDARD = LVCMOS33 ;
##############################################################################
# Debug Port # JA1
##############################################################################
NET "DEBUG[0]" LOC = "B12" |IOSTANDARD = LVCMOS33;
NET "DEBUG[1]" LOC = "B11" |IOSTANDARD = LVCMOS33;
##############################################################################
# DCM/PLL/BUFPLL positions
##############################################################################
#INST "PCLK_GEN_INST" LOC = "DCM_X0Y3";
#INST "PLL_OSERDES" LOC = "PLL_ADV_X0Y1";
#INST "ioclk_buf" LOC = "BUFPLL_X1Y0";
###########################################
# Timing Constraints
###########################################
NET "clk50m_bufg" TNM_NET = "TNM_CLK50M";
TIMESPEC "TS_CLK50M" = PERIOD "TNM_CLK50M" 50 MHz HIGH 50 % PRIORITY 0 ;
NET "pclk" TNM_NET = "TNM_PCLK";
TIMESPEC "TS_PCLK" = PERIOD "TNM_PCLK" 108 MHz HIGH 50 % PRIORITY 0 ;
NET "pclkx2" TNM_NET = "TNM_PCLKX2";
TIMESPEC "TS_PCLKX2" = PERIOD "TNM_PCLKX2" TS_PCLK * 2;
NET "pclkx10" TNM_NET = "TNM_PCLKX10";
TIMESPEC "TS_PCLKX10" = PERIOD "TNM_PCLKX10" TS_PCLK * 10;
#
# Multi-cycle paths
#
TIMEGRP "bramgrp" = RAMS(enc0/pixel2x/dataint<*>);
TIMEGRP "fddbgrp" = FFS(enc0/pixel2x/db<*>);
TIMEGRP "bramra" = FFS(enc0/pixel2x/ra<*>);
TIMEGRP "bramgrp" = RAMS(enc1/pixel2x/dataint<*>);
TIMEGRP "fddbgrp" = FFS(enc1/pixel2x/db<*>);
TIMEGRP "bramra" = FFS(enc1/pixel2x/ra<*>);
TIMESPEC "TS_ramdo" = FROM "bramgrp" TO "fddbgrp" TS_PCLK;
TIMESPEC "TS_ramra" = FROM "bramra" TO "fddbgrp" TS_PCLK;

############################
# TMDS pairs on the top
############################
NET "TMDS2(0)" LOC = "R3" |IOSTANDARD = TMDS_33 ; # Blue
NET "TMDSB2(0)" LOC = "T3" |IOSTANDARD = TMDS_33 ;
NET "TMDS2(1)" LOC = "T4" |IOSTANDARD = TMDS_33 ; # Red
NET "TMDSB2(1)" LOC = "V4" |IOSTANDARD = TMDS_33 ;
NET "TMDS2(2)" LOC = "N5" |IOSTANDARD = TMDS_33 ; # Green
NET "TMDSB2(2)" LOC = "P6" |IOSTANDARD = TMDS_33 ;
NET "TMDS2(3)" LOC = "T9" |IOSTANDARD = TMDS_33 ; # Clock
NET "TMDSB2(3)" LOC = "V9" |IOSTANDARD = TMDS_33 ;
NET "TMDS1(0)" LOC = "D8" |IOSTANDARD = TMDS_33 ; # Blue
NET "TMDSB1(0)" LOC = "C8" |IOSTANDARD = TMDS_33 ;
NET "TMDS1(1)" LOC = "C7" |IOSTANDARD = TMDS_33 ; # Red
NET "TMDSB1(1)" LOC = "A7" |IOSTANDARD = TMDS_33 ;
NET "TMDS1(2)" LOC = "B8" |IOSTANDARD = TMDS_33 ; # Green
NET "TMDSB1(2)" LOC = "A8" |IOSTANDARD = TMDS_33 ;
NET "TMDS1(3)" LOC = "B6" |IOSTANDARD = TMDS_33 ; # Clock
NET "TMDSB1(3)" LOC = "A6" |IOSTANDARD = TMDS_33 ;


Please help me in solving this issue. Thanks
            vtc_demo.v ‏21 KB