vivado属性IOB为false不会从ilogic中删除寄存器

嗨，在vhdl我有属性iob设置为true，但在一块板上我需要删除它们，所以在xdc文件中添加：“set property IOB FALSE [get cells -hierarchical [list”* data_in_iob_reg *“]]”命令是
此寄存器的工作和属性已更改，但在完成路由后，此寄存器仍在IOB内部打包。
我的主板使用的是virtex 7v2000。
Vivado版本是2013.3，项目在synplify中合成。
我该如何解决这个问题？我已尝试在寄存器上取消放置_，但它也删除了端口位置（属性位置在IOBUFT上设置，在hdl源代码中实例化，我的寄存器输出连接到该位置）。从vhdl中移除属性
这不是一种简单（快速）的方式，因为那时我需要为许多电路板和virtex技术编写适当的约束。
但我想只删除1个特定的板.Chris



以下为原文

Hi,

in vhdl i have property iob set on true, but on one board i need to remove them, so in xdc file add:
"set property IOB FALSE [get cells -hierarchical [list "*data_in_iob_reg*"]]"
command is working and properties for this registers are changed, but after routing is done this registers are still packed inside IOBs. My board is using virtex 7v2000. Vivado version is 2013.3, project is synthesized in synplify.  How can I fix that?

I've tried to unplace_cell on my registers, but it's removing also port location (property location is set on IOBUFT which is instantiated in hdl source code, to which my register output is connected).

Removing property from vhdl is not an easy (and fast) way, because then i need to write apropriate constraints for many boards and virtex technologies. But i want to remove them only for 1 particular board.

Chris