怎么在spartan3中将输入FF推送到IOB

您可以尝试“IOB”约束。
请注意，如果输入板和第一个寄存器之间有任何逻辑，则无法将该寄存器打包到IOB。
VHDL语法ExampleDeclare VHDL约束如下：attribute iob：string;如下指定VHDL约束：{component_name | entity_name | label_name}的属性iob：{component | entity | label}为“{TRUE | FALSE | AUTO}”;
其中•TRUE允许将触发器或锁存器拉入IOB
•FALSE表示不将其拉入IOB•仅XST使用AUTO。
XST考虑时序约束并自动决定是否推动触发器进入IOB。有关基本VHDL语法的更多信息，请参阅第3章中的“VHDL”.Verilog语法示例按如下方式指定Verilog约束：（* IOB =“{TRUE
| FALSE | AUTO}“*）请参阅上面”VHDL语法示例“中的值定义。有关基本Verilog语法的更多信息，请参阅第3章中的”Verilog“。
有关这方面的更多信息可以在Constraint Guide中找到。



以下为原文

You could try the "IOB" constraint. Note that if there is any logic between the input pad and first register, you could not pack this register to IOB.
 
VHDL Syntax Example
Declare the VHDL constraint as follows:
attribute iob: string;
Specify the VHDL constraint as follows:
attribute iob of {component_name|entity_name|label_name}:
{component|entity|label} is “{TRUE|FALSE|AUTO}”;
where
• TRUE allows the flip-flop or latch to be pulled into an IOB
• FALSE indicates not to pull it into an IOB
• AUTO is used by XST only. XST takes into account timing constraints and
automatically decides to push or not to push flip-flops into IOBs
For more information on basic VHDL syntax, see “VHDL” in Chapter 3.
Verilog Syntax Example
Specify the Verilog constraint as follows:
(* IOB = “{TRUE|FALSE|AUTO}” *)
See value definitions in “VHDL Syntax Example” above.
For more information on basic Verilog syntax, see “Verilog” in Chapter 3.
 
More info on this could be found in the Constraint Guide.
 
 
 

嗯......还是不行。
它将强制翻牌进入输出IOB，而不是输入IOB，就像我想要的那样。
库ieee;使用ieee.std_logic_1164.all;实体测试是端口（时钟：在std_logic中; a，b，c：在std_logic中; dout1：输出std_logic; dout2：输出std_logic）;结束测试;测试的架构test_arch是信号a_reg
：std_logic;
- 推进IOB !!!
属性iob：string;
a_reg的属性iob：signal是“true”;
如果rising_edge（时钟）然后a_reg结束if，则开始进程（时钟）开始;
结束过程; 
dout1 dout2 end test_arch;



以下为原文

Hmmm... still isn't working.  It will force the flop into the output IOB, not the input IOB like I want it to.

 
library ieee;
use ieee.std_logic_1164.all;

entity test is
  port(
    clock   : in  std_logic;
    a, b, c : in  std_logic;
    dout1   : out std_logic;
    dout2   : out std_logic
    );
end test;

architecture test_arch of test is

  signal a_reg : std_logic; -- push into the IOB!!!

  attribute iob: string;
  attribute iob of a_reg: signal is "true";
  
begin

  process(clock)
  begin
    if rising_edge(clock) then
      a_reg <= a;
    end if;
  end process;

  dout1 <= a_reg;
  dout2 <= a and b and c;

end test_arch;

您可以使用“BEL”约束将寄存器放入IOB的输入寄存器中。
对于您的特定示例，您可以在源代码中添加以下行： 
属性bel：string;
a_reg的属性bel：signal是“IFF1”;
干杯，
吉姆
干杯，吉姆



以下为原文

You can use "BEL" constraint to place the register in the input register of IOB. For your particular example, you can add the lines below in your source code:
 
  attribute bel: string;
  attribute bel of a_reg: signal is "IFF1";
 
Cheers,
Jim
 
Cheers,
Jim

另一种方法是尽可能增加一些寄存器
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以下为原文

another way is to put some additional registers if possible------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
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