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大家好,
我有一个流水线模块,花费几个时钟周期设置管道,在准备的某些阶段,我可以使用两个不同的寄存器来设置第三个(因为它们具有相同的值),如果我在我的代码中尝试不同的方法它 具有LUT和时序影响(特别是在地点和路线上),但显然没有功能影响。 我有一些这样的,所以排列变得太大,无法手动关注。 有没有办法告诉vivado它可以从两个源寄存器中进行选择,以便它可以相应地进行优化? 例如... reg [31:0] fred; reg [31:0]乔; reg [31:0] bill; if(i == 0)开始 弗雷德 非常感谢, 李。 以上来自于谷歌翻译 以下为原文 Hi All, I have a pipelined module that spends a few clock cycles setting up the pipeline, at some stages of the prep I could use two different registers to set a third (since they have the same value), if I try the different approaches in my code it has a LUT and a timing impact (especially on place & route) but obviously no functionality impact. I have a few of these, so the permutations become too large to manually keep an eye on. Is there a way to tell vivado that it can choose from two source registers so it can optimise accordingly? For example... reg [31:0] fred;reg [31:0] joe;reg [31:0] bill;if (i == 0) begin fred <= a + b; i <= 1;end else if (i == 1) begin joe <= fred; i <= 2;end else if (i == 2) begin bill <= *** fred, or joe ... whichever is "best" ***end Many thanks, Lee. |
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如果我可以这么说的话,我认为你需要对管道设计进行简短的回顾。
- 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 I think you need a short refresher on pipeline design, if I may say so.- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
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谢谢Muzaffer - 非常有帮助!这纯粹是一些示例代码来说明我的观点。
我的实际设计工作得比你好! 我只是想尽可能高效。 以上来自于谷歌翻译 以下为原文 Thanks Muzaffer - very helpful! It was purely some sample code to illustrate my point. My actual design is working rather well thankyou! I'm just trying to be as efficient as possible. |
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李,
什么是'我'? 我可以将你的代码解释为'我'是一个状态机变量。 它看起来像那样。 但你说管道。 所以,我想也许'我'是一个genvar? 如果我们有任何帮助,您需要在示例中添加更多上下文。 问候, 标记 以上来自于谷歌翻译 以下为原文 Lee, What is 'i'? I could interpret your code as 'i' being a state-machine variable. It sort of looks like that. But you said pipeline. So, I'm thinking perhaps 'i' is a genvar? You'll need some more context in your example if we're to be of any help. Regards, Mark |
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好吧..我以为我只提供了一个简单的例子来说明我的观点,但很明显我刚刚让它变得更复杂!
让我解释一下背景...... 我有一个用一组状态初始化的模块,然后通过多次迭代处理(在一组工作寄存器中保持更新状态),然后最终更新初始状态值。 在处理过程中有一些相当复杂的计算。 为了满足我的时序需求,我已将计算结果分开并执行多个时钟周期,但仍然在每个周期将更新提供给工作寄存器(这是可能的,因为某些输入在先前的周期中可用。)因此,这是流水线的(除非 我在这里有错误的定义) - 完成计算需要3个时钟,但我在每个周期都提供一个完整的计算。 但是,在产生第一次更新之前,需要对管道进行初始化(种子?),并且由于各个阶段依赖于先前的,因此我使用状态机来处理初始化。 为了使问题更加复杂......尽管我的计算方法已经分开了,但仍然需要一些三输入加法器以及一些其他逻辑,如果我在状态机上做出这些依赖,则不可能满足时序,因此我将它们拉出来 通过在状态机的前几个阶段中操纵输入值来保持计算的正确性。 它工作得很漂亮,我对结果非常满意。 然而,这导致了一个问题......在前两个状态机准备阶段,我有一个“工作”寄存器和一个实际包含相同值的“初始化”寄存器(它们稍后会发散,但这并不重要 。) 因此,如果我想将该值分配给另一个寄存器,我可以使用任一源寄存器,它们都可以正常工作。 当我试验这个时,根据我的选择,我会看到不同的时间和LUT计数。 哪个好。 但现在看来,我正在进行手动优化,能够告诉Vivado可以自由选择喜欢的寄存器。 那可能吗? 或者我仅限于手动执行此操作? 谢谢, 李。 以上来自于谷歌翻译 以下为原文 Ok .. I thought i'd just provided a minimal example to illustrate my point, but it pretty clear that I've just made it more complex! Let me explain more about the background... I have a module that is initialised with a set of state, this is then processed through a number of iterations (keeping the updating state in a set of working registers) and then ultimately updates the initial state values. During the processing there are some fairly complex calculations. In order to meet my timing needs I have pulled the calcs apart and execute over multiple clock cycles, but still deliver the update to the working registers each cycle (which is possible because some of the inputs are available in prior cycles.) Hence this is pipelined (unless I have the wrong definition here) - it takes 3 clock to do the full calcs, but I deliver an full calc each cycle. However, the pipeline needs to be initialised (seeded?) before the first update can be produced, and since the various stages are dependent on the previous I used a state machine to handle the initialisation. To further complicate matters ... despite pulling my calcs apart there are still a number of three-input-adders required with some further logic, and it's not possible to meet the timing if I make these dependent on the state machine, hence I pull them out and keep the calcs correct by manipulating the input values during the first few stages of the state machine. It works beautifully and I'm very pleased with the results. However this then leads to the question... during the first two state machine prep stages, I have both a "working" register, and an "initialisation" register that actually contain the same value (they will diverge later, but that's not important.) So if I want to assign that value to another register I can use either of the source registers, they both work fine. When I experiment with this I see different timings and LUT counts depending on the choice I make. Which is fine. But it now seems that I am making a manual optimisation, where it would be nice to be able to tell Vivado that it's free to choose whichever register it likes. Is that possible? Or am I limited to doing this manually? Thanks, Lee. |
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ViVado无法进行您想要的选择。
最好的办法是根据定义或参数编写编译时选择,并自动选择过程,即运行所有版本并以编程方式选择最佳时序/区域。 - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 ViVado has no facility to do the selection you want. Your best bet is to code a compile time selection based on defines or parameters and automate the process of selection ie run all versions and pick the best timing/area programmatically. - Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
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