使用PLL_ADV从CLK_IN时VCO频率远高于Spartan-6允许的频率

嗨！我正在试验用作解串器的Spartan-6。
我无法100％无错误，所以不幸的是我需要更仔细地分析我的代码的行为（以及我在那里使用的原语：ISERDES，ODELAY2和校准机制 - 也许他们给了我很多时间）。
为此，我想使用非常慢的时钟信号（使用示波器更容易观察，更多时间记录一些值）。
此时我遇到了一个问题：我使用PLL_ADV从CLK_IN中产生三个时钟。
PLL具有反馈环路（与图3-5中所示的完全相同 -  ug382_c3_04_081710）。
在此设置中，只要我将CLKOUT0_DIVIDE设置为大于'1'的任何值，我的VCO频率远高于Spartan-6允许的频率。
在选择PLL_ADV参数时我依赖于CoreGenerator，但在计算数字时忽略了反馈循环，因此对我来说没用（至少我无法弄清楚它对我有什么帮助）。
我将欣赏一些关于如何使用CLK_IN =（比如）40 MHz同时输出时钟为80 MHz，10 MHz和5 MHz的提示，同时确保f_VCO处于适当的范围内。
我正在重复这个问题，因为我已经标记为已解决的原始线程可能没有引起太多关注。
对不起双重帖子，如果这是问题.RegardsPawel



以下为原文

Hi!

I am experimenting with Spartan-6 used as a deserializer. I cannot make it 100% error-free so unfortunately I need to analyze closer the behaviour of my code (and the primitives I use there: ISERDES, ODELAY2 and the callibration mechanism -- maybe they are giving me hard time). To this end I would like to work with very slow clock signals (easier to observe things with oscilloscope, more time to record some values). At this point I hit on a problem:

I am using the PLL_ADV to make three clocks out of CLK_IN. The PLL has a feedback loop (exactly like the one shown on Fig. 3-5 -- ug382_c3_04_081710). In this set-up anytime I set CLKOUT0_DIVIDE to anything larger than '1', I get the VCO frequency much higher than allowed for Spartan-6. While selecting PLL_ADV params I relied on CoreGenerator, but it ignores the feedback loop while calculating the numbers, so is useless for me (at least I cannot figure out how could it help me) .

I will appreciate some hints on how do I work with CLK_IN = (say) 40 MHz while the output clocks are 80 MHz, 10 MHz, and 5 MHz, while making sure that the f_VCO is in proper range.

I am repeating this question since chances are that the original thread that I already marked as solved does not attact too much attention. Sorry for double posts in case this is problem.

Regards

Pawel