ISE和EDK 12.3错误：PhysDesignRules：1452不支持的PLL_ADV配置

一些原语_do_有关于什么可以驱动特定基元上的特定引脚的要求。
但这是特定于设备的。
您定位的是哪种设备？
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以下为原文

some primitives _do_ have requirements as to what can drive a particular pin on a particular primitive.  This is device-specific, though.
 
Which device are you targeting?
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嗨，谢谢你的回复。
我是如此接近，但到目前为止..我正在使用一个初学者6 XC6LSX25l -1L（低功率版本）。我有一个项目需要非常低的功耗。我必须使用ISE才能使用功率评估工具。我
项目在SDK下编译得很好
但在ISE下失败，时钟输入（全局时钟线GCLK28）为PLL（我的系统时钟源）供电。正如我所说.ISE为所有连接LPDDR存储器的线路附加“OUT”。为避免这种情况，我取消选中
-iobuf。但是它无法在clock_sys输入上放置缓冲区。
所以我实例化了一个BUFG原语。它现在映射所有并且只在地点和路线的末尾映射它无法连接那条简单的线路。
有什么办法呢...我还没找到SOLID文件！
..最糟糕的是，从版本到版本，似乎解决方案发生变化，不再起作用了！
我不知道如何在我的miroblaze mem中使用LPDDR mem作为缓存，似乎基本系统构建器不支持它。只有dd2和dd3 ..



以下为原文

Hi and thanks for the reply .
Im so close and yet so far .. I am using a startan 6 XC6LSX25l -1L( low power version) .I have a project that requires very low power comsumption .I have to use ISE in order to use the power evaluation tools .My project compiles well under SDK
but fails under ISE  with the clock input  ( a global clock line GCLK28) feeding the PLL( my system clock gen) .As i said .ISE appends an "OUT" to all the lines interfacing a LPDDR memory .To avoid this i unchecked the -iobuf .But then it  fails to put buffer on the clock_sys input .
So i instantiated a BUFG primitive .It now maps all and only at the end of place and route it fails to connect that simple line .
What is the way to do this .. I have not found a SOLID document ! ..The worst is that from version to version it seems that solutions changes and don't work any more !
 
Incidently how can i use LPDDR mem as cache in my miroblaze mem ,It seems that the base system builder doesn't support it .Only dd2 and dd3 ..

任何解决方案或进一步的想法？
我得到同样的错误，虽然在MIG [3.3在ISE12.1（lin）“M.53d]中生成的模块中有所下降 
片外差分时钟被馈送到IBUFGDS，单端结果由此送到DCM：
[来自生成的文件：memc5_infrastructure.v] IBUFGDS＃（。DIFF_TERM（“TRUE”））u_ibufg_sys_clk（.I（sys_clk_p）,. IB（sys_clk_n）,. O（sys_clk_ibufg））;
PLL_ADV＃（/ *各种参数* / 
）u_pll_adv（.CLKFBIN（clkfbout_clkfbin）,. CLKINSEL（1'b1）,. CLKIN1（sys_clk_ibufg），[...] 
）;
收益率：
>错误：PhysDesignRules：1452  - 不支持的PLL_ADV配置。
信号
> PLL_ADV comp> SF2 / MC / memc5_infrastructure_inst / u_pll_adv的CLKIN1引脚上的SF2 / MC / memc5_infrastructure_inst / sys_clk_ibufg不是由IOB，BUFIO2，BUFIO2_2CLK，BUFG驱动的，
>此连接的BUFGCTRL或DCM和路由不可用。
我确实阅读了UG615，其中对CORE生成器说“NO”作为设计输入方法并且“放入所有I / O 
设计顶层的组件......“
再次，MIG为我做了这一切。
干杯！
HWN



以下为原文

any solution or further thoughts to this?
 
i am getting this same error, albeit down in modules generated by MIG [3.3 in ISE12.1(lin) "M.53d] where
  an off-chip differential clock is fed to an IBUFGDS and the single ended result thence to the DCM:
 
[from generated file: memc5_infrastructure.v]
      IBUFGDS #
        (
         .DIFF_TERM    ("TRUE")
         )
        u_ibufg_sys_clk
          (
           .I  (sys_clk_p),
           .IB (sys_clk_n),
           .O  (sys_clk_ibufg)
           );

    PLL_ADV #
        ( /*various params*/
        )
        u_pll_adv
          (
           .CLKFBIN     (clkfbout_clkfbin),
           .CLKINSEL    (1'b1),
           .CLKIN1      (sys_clk_ibufg),
                  [...]
       );
 
yields:
> ERROR:PhysDesignRules:1452 - Unsupported PLL_ADV configuration. The signal
> SF2/MC/memc5_infrastructure_inst/sys_clk_ibufg on the CLKIN1 pin of PLL_ADV comp
> SF2/MC/memc5_infrastructure_inst/u_pll_adv is not driven by an IOB, BUFIO2, BUFIO2_2CLK, BUFG,
> BUFGCTRL, or DCM and routing for this connectivity is not available.
 
i did read UG615, where it says "NO" to CORE generator as a design entry method and "Put all I/O
  components on the top-level of the design..."
again, MIG did this all for me.
 
cheers!
hwn