DCM不同的时钟信号会改变clk0的频率

我在DCM时钟频率方面遇到了一些麻烦。
我创建了两个具有相同时钟输入的相同DCM，我使用这些DCM的clk0输出作为两个相同模块的输入。
但是，当我更改clkfx_multiply或clkfx_divide参数时，有时这会改变clk0的频率。
根据我的理解，这些参数应该只影响clkfx输出。
clk0在仿真中都是相同的，但是当在FPGA上实现时，它们是不同的。
这有什么特别的原因吗？
另外，100Mhz inputclkfx_multiply为9 andclkfx_divide为5并不能给我180Mhz时钟（它在模拟中但不在FPGA上），但是clkfx_multiply为9且clkfx_divide为10（模拟时为90MHz，FPGA上为180Mhz）。
以前有没有人遇到过这些问题？



以下为原文

I am having some trouble with DCM clock frequencies.

I have created two identical DCMs with the same clock input and I am using the clk0 output from these DCMs as the input to two identical modules.

However when I change the clkfx_multiply or the clkfx_divide parameters, sometimes this will change the frequency of the clk0 out. From my understanding, these parameters should only affect the clkfx output.

Both clk0 are the same in simulation but when implemented on an FPGA, they differ.

Is there any particular reason for this?

Also with a 100Mhz input clkfx_multiply of 9 and clkfx_divide of 5 does not give me a 180Mhz clock (it does in simulation but not on the FPGA), however clkfx_multiply of 9 and clkfx_divide of 10 does (90MHz in simulation but 180 Mhz on FPGA). Has anyone ever come accross these problems before?