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姜薇

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[问答]

我的BRAM在哪里?

嗨,大家好,
我有一个Zynq 7020设计,在某处使用两个块公羊;
使用Vivado(2016.2)块内存生成器生成(每个内存为32位宽,100k深)。
合成后,利用率如下:
这是我所期待的。
但是,在实现之后,它看起来像这样:
......现在我想知道我的记忆在哪里:-)他藏在哪里(在Zynq)?
Vivado在哪个报告中告诉我它在使用BRAM时做了什么?
利用率报告还说使用了0%的BRAM ...
干杯!
马里奥

以上来自于谷歌翻译


以下为原文

Hi Guys,

I have a Zynq 7020 design that somewhere uses two block-rams; generated using Vivado's (2016.2) Block Memory Generator (each memory is 32bit wide and 100k deep).
After synthesis, the utilization is like this:

This is what I'd expect. However, after implementation, it looks like that:

...and now I'm wondering where my memory went :-) Where does he hide it (in the Zynq)? In which report does Vivado tell me what it's doing with the BRAMs? The utilization report also says that 0% BRAMs are used...

Cheers!
Mario

回帖(7)

石俊梅

2018-10-26 15:18:37
你好@ mauererm
您可以使用ARhttp://www.xilinx.com/support/answers/58616.html中描述的技术来查找修剪的原因。
谢谢,迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
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在原帖中查看解决方案

以上来自于谷歌翻译


以下为原文

Hi @mauererm
 
You can use the technique described in AR http://www.xilinx.com/support/answers/58616.html to find the reason for the trimming. 
Thanks,
Deepika.
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石俊梅

2018-10-26 15:29:09
你好@ mauererm
您是否在设计中正确连接了IP?
看起来实现工具正在修剪BRAM实例。
请打开已实现的设计,然后转到编辑 - >查找并搜索设计中是否有BRAM类型的单元格。
如果结果为空,则打开合成设计并检查BRAM输入和输出是否在原理图中正确连接。
谢谢,迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星)

以上来自于谷歌翻译


以下为原文

Hi @mauererm
 
Did you connect the IP properly in the design? It looks like implementation tool is trimming the BRAM instances.
 
Please open implemented design and go to Edit -->find and search if there are any cells of type BRAM in the design. If the results are empty then open synthesized design and check if the BRAM inputs and outputs are connected properly or not in schematic.
 
 
Thanks,
Deepika.
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胡皓

2018-10-26 15:40:35
嗯,实施设计中没有BRAM,但原理图看起来不错;
它就在那里并且有线......

以上来自于谷歌翻译


以下为原文

Hmm, no BRAM in implemented design, but schematic looks good; it's all there and wired...
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石俊梅

2018-10-26 15:52:10
你好@ mauererm
您可以使用ARhttp://www.xilinx.com/support/answers/58616.html中描述的技术来查找修剪的原因。
谢谢,迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星)

以上来自于谷歌翻译


以下为原文

Hi @mauererm
 
You can use the technique described in AR http://www.xilinx.com/support/answers/58616.html to find the reason for the trimming. 
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
举报

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