为什么我无法将其直接输入GCLK并使用它来驱动异步fifo输入时钟？

你好
没有FIFO不能在门控时钟上工作。
FIFO Generator仅适用于自由运行的写和读时钟。
赛灵思
不建议通过操作rd_clk和wr_clk来控制内核如果需要此功能来进行FIFO操作，我们建议使用写使能（wr_en）和读使能（rd_en）信号。
检查下面的文档，清楚地提到这一点。
http://www.xilinx.com/support/documentation/ip_documentation/fifo_generator/v9_3/pg057-fifo-generator.pdf
问候，萨蒂什-----------------------------------------------
--- --------------------------------------------请注意
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
---------------------------- ---------------------
----------------------



以下为原文

Hi
 
No the FIFO cannot work on a gated clock.
 
 

 

 
Check below doc which clearly mentions this.
 
http://www.xilinx.com/support/documentation/ip_documentation/fifo_generator/v9_3/pg057-fifo-generator.pdf
 
Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

嗨，
有关使用自由运行时钟访问FIFO的更多视图，请参阅下面的相关讨论
http://forums.xilinx.com/t5/System-Logic/FIFO-Generator-8-3-problem/td-p/523811
问候，
Vanitha
--------------------------------------------------
-------------------------------------------请在发布前进行谷歌搜索，
您可能会找到相关信息。请留下帖子 - “接受为解决方案”，如果提供的信息有用且回复，请给予赞誉



以下为原文

Hi,
 
For more views on accessing FIFO with out free running clock please go through below relavant discussion
http://forums.xilinx.com/t5/System-Logic/FIFO-Generator-8-3-problem/td-p/523811
 
Regards,
Vanitha
---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

如今，FPGA的1 MHz非常慢。
由于您有足够的时间来处理数据采样，因此使用异步板级时钟（例如50 MHz）来采样1 MHz门控时钟并为内部逻辑创建时钟使能是非常有意义的。
如果您已经计划在FIFO的输出端使用这样的时钟，则只需要确保它足够快，以便在450ns数据有效窗口期间检测边沿并对数据进行采样。
一些技巧：
1）使用至少3个触发器来制作同步器/延迟电路以检测时钟上的边沿。
通过对移位寄存器中的最后两个触发器进行采样来检测时钟上的边沿。
2）如果要对接近输入时钟边沿的数据进行采样，还要在输入数据上添加一个3级流水线，这样时钟使能将查看延迟的数据与检测时间的数量大致相同。
时钟边缘。
如果仍需要FIFO，则可以使用同步（公共时钟）FIFO并使用时钟边沿检测脉冲作为该FIFO的写入输入。
-  Gabor



以下为原文

1 MHz is really slow for an FPGA these days.  Since you have so much time around the clock edge to sample the data, it really makes sense to use an asynchronous board-level clock, say 50 MHz, to sample the 1 MHz gated clock and create a clock enable for internal logic.  If you already have such a clock you were planning to use on the output side of the FIFO, you just need to be sure it's fast enough to allow you to detect the edge and sample the data during the 450ns data valid window.
 
Some tips:
 
1) Use at least 3 flip-flops to make a synchronizer / delay circuit to detect edges on the clock.  Detect edges on the clock by sampling the last two flip-flops in the shift register.
 
2) If you want to sample the data closer to the incoming clock edge, also add a 3-stage pipeline on the input data so the clock enable will be looking at data that's been delayed by about the same amount as the time to detect the clock edge.
 
If you still need a FIFO, then you can use a synchronous (common clock) FIFO and use the clock edge detection pulse as the write input to that FIFO.
-- Gabor