[问答]

如何处理各自带来自己时钟的不同视频源

问答对人有帮助，内容完整，我也想知道答案 0 大家好，我正在开发一种Spartan 3设计，旨在将来自不同源的视频流切换到DSP和/或不同的视频输出。两个视频通道应并行路由。我的问题始于六个视频源中的每一个都带有自己的时钟（74.25MHz或148.5MHz）。所有时钟都连接到FPGA上的时钟输入。配置示例： 1）带有时钟A的视频输入A被路由到输出X. 2）带有时钟B的视频输入B被路由到输出Y. 3）带有时钟A的视频输入A被路由到输出X和Y. 4）更多组合...... 在输出数据之前，会发生一些处理，例如同步生成和格式检测。我需要从不同的时钟驱动输出。我的第一种方法如下：通过多路复用器和BUFG将当前选择的输入时钟路由到DCM。从该DCM驱动下游逻辑。实例化两个这样的DCM，每个内部视频通道一个。对于一个源和几个输出，这工作正常。我的问题是：在不同来源之间切换DCM的输入时钟是个好主意吗？如何将输入数据（与输入时钟相关，而不是DCM输出时钟）输入到DCM驱动的逻辑中？如何从一个DCM驱动的逻辑驱动物理输出（IOB）并切换到另一个DCM驱动的逻辑？通过内部三态总线？我也尝试使用一个简单的多路复用矩阵来切换视频数据，但这并没有真正起作用，因为我根本无法控制输出时序。任何帮助表示赞赏。马库斯以上来自于谷歌翻译以下为原文 Hi all, I'm working on a Spartan 3 design which is intended to switch video streams from different sources to a DSP and/or different video outputs. Two video channels shall be routed in parallel. My problem starts with the fact that each of the six video sources brings its own clock (74.25MHz or 148.5MHz). All clocks are hooked up to clock inputs on the FPGA. Example configurations: 1) Video input A with clock A is routed to output X 2) Video input B with clock B is routed to output Y 3) Video input A with clock A is routed to output X and Y 4) More combinations... Before the data is output, some processing occurs, like sync generation and format detection. I need to drive the outputs from different clocks. My first approach is as follows: Route the currently selected input clock to a DCM via a mux and a BUFG. A downstream logic is driven from that DCM. Two such DCMs are instatiated, one for each of the internal video channels. For ONE source and several outputs this works fine. My questions are: Is it a good idea to switch the input clocks at the DCM between the different sources? * How do I get the input data (which relates to the input clock, not the DCMs output clock) into the logic that is driven from the DCM? * How do I drive the physical output (IOBs) from the logic driven by one DCM and switch to logic driven by the other DCM? By an interal tristated bus? I also tried using a simple mux matrix to switch the video data, but this does not really work because I can't control the output timing at all. Any help is appreciated. Markus 0
2019-6-5 09:53:03　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答举报杨艳相关推荐 • 请问时钟抖动如何处理？ 3419 • 如何处理好跨时钟域间的数据呢 1353 • STM32的SysTick时钟源是来自Cortex系统定时器吗 572 • 如何处理具有多个可能中断源的中断 1550 • rk3288硬解1080P的H264的视频顶部出现绿条该如何处理 1228 • TF数据线和时钟线等长如何处理 3832 • LabVIEW实时视频处理 3287 • STM32的SysTick时钟源到底是从哪来呢 970 • MCU功耗来自何处？ 1900 • 基于DSP+FPGA的视频处理模块的设计与实现 2416 2个回答

答案对人有帮助，有参考价值 0 时钟切换通常是一个坏主意。标准视频输入多路复用器包括一个短FIFO，用于将输入数据移动到一个公共的“系统”时钟，后跟一个同步多路复用器。在您的情况下，如果所有视频都以2个频率之一运行，但是这些来源都是异步的，你似乎有意义具有标准的148.5 MHz系统时钟。如果可以使这个时钟变小比最快的输入时钟快一点，那么你只需要非常短的FIFO。除此以外 FIFO深度取决于视频的行长度（假设您只写有效视频到FIFO）。在FIFO之后，数据总是伴随着时钟能够处理数据速率的差异。输出视频将始终被驱动通过系统时钟，可能使用74.25 MHz的50％占空比时钟使能视频类型。您将再次使用FIFO来确保输出线由于时钟频率的轻微差异（FIFO欠载）而没有中断。问候，的Gabor - Gabor 以上来自于谷歌翻译以下为原文 Clock switching is generally a bad idea. The standard video input mux consists of a short FIFO to move the input data onto a common "system" clock followed by a synchronous multiplexer. In your case if all video is running at one of 2 frequencies, but the sources are all asynchronous, it would seem to make sense that you would have a standard 148.5 MHz system clock. If it is possible to make this clock a tiny bit faster than the fastest input clock then you need only very short FIFO's. Otherwise the FIFO depth depends on the line length of the video (presuming you only write active video to the FIFO). After the FIFO the data is always accompanied by a clock enable to deal with differences in data rate. Output video would always be driven by the system clock, possibly using a 50% duty cycle clock enable for the 74.25 MHz video type. Again you would use a FIFO to make sure that the output lines are not interrupted due to slight differences in clock frequency (FIFO underrun). Regards, Gabor -- Gabor

2019-6-5 10:10:10 评论举报杨玲

答案对人有帮助，有参考价值 0 如果我理解正确，您可以尝试通过标准I / O引脚将所有输入连接到内部多路复用器（异步）。该多路复用器通过内部逻辑控制。该多路复用器的输出被馈送到另一个I / O引脚并从FPGA馈电并重新路由。使用GCLK输入作为时钟。您可以通过多路复用器的放置约束来控制延迟，在切换期间保持系统处于视频信号的复位状态。基本上它是一个外部视频多路复用器，但您正在使用FPGA I / O. 我以前用数字音频信号（49MHz）完成了这项工作并且运行良好，你的高速视频信号可能需要一些放置限制。问候以上来自于谷歌翻译以下为原文 If I understand you correctly, you could try bringing all the inputs in via standard I/O pins to an internal mux (async). This mux is controlled via your internal logic. The output of this mux is fed to another I/O pin and fed off the FPGA and routed back in. Use a GCLK input for clock. You can control delays with placement constraints of the muxes, During switching hold the system in reset that handles the video signals. Basically its an external video mux but you are using the FPGA I/O. I've done this before with digital audio signals (49MHz) and it worked well, your higher speed video signals will probably require some placement constraints. Regards

2019-6-5 10:44:27 评论举报王璨