请问有几个GTP可以与usrclk2共享DCM

嗨，
您可以使用您提到的配置。
但是，还有另一面，当您为所有GTP使用相同的TXUSRCL时，您可能会看到时序违规。
请对用户时钟应用时序约束，看看是否可以满足时序要求。
问候，
克里希纳
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以下为原文

Hi,
 
You can use the configuration that you mentioned. But, there is a flip side to it, you may see timing violations when using the same TXUSRCLks for all GTPs.
 
Please apply timing constraints on the user clocks and see if you can meet the timing.
 
Regards,
Krishna
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克里希纳，
谢谢。
我将时序约束添加到双tile0_GTP0的gtpclkout0（0/1）。
refclk是148.5 MHz（因此usrclk20将是74.25 MHz）并且约束条件满足。
仍然从tile0_GTP1收到的数据有错误。
我观察到的另一件事是我不能使用gtpclkout0（0）来生成rxusrclk20，但是我可以使用rxrecclk0而不是gtpclkout0（1）来生成rxusrclk20并正确地从tile0_GTP0恢复数据。
问候，
马兹



以下为原文

Krishna,
 
Thanks. I added timing constraint to gtpclkout0(0/1) of the dual tile0_GTP0. The refclk is 148.5 MHz (and so the usrclk20 will be 74.25 MHz) and the constraints meet. Still the data received from tile0_GTP1 has errors.
 
Another thing that I observed was that I cannot use gtpclkout0(0) to generate rxusrclk20, but I can use rxrecclk0 instead of gtpclkout0(1) to generate rxusrclk20 and recover data from tile0_GTP0 correctly.
 
Regards,
Maz

gtpclkout0（0）用于Tx，gtpclkout0（1）用于Rx。
你发现设计在模拟中工作吗？
如果您使用逗号对齐，请检查此模块的状态信号以开始。
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以下为原文

gtpclkout0(0) is for Tx and gtpclkout0(1) is for Rx.

Do you find the design working in simulation? if you are using comma alignment, check the status signals of this module to start with.------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

Srinadh，
谢谢。
gtpclkout0（0）用于Tx，gtpclkout0（1）用于Rx。
来自UG386，
据说REFCLKPLL可以通过gtpclkout0（0）输出到FPGA逻辑，但你是对的。
如果我们“只”考虑频率，那么这个时钟与我设计中的rxrecclk相同。
你发现设计在模拟中工作吗？
如果您使用逗号对齐，请检查此模块的状态信号以开始。
是的，tile0_gtp1在使用gtpclkout0（1）和rxrecclk0（我不确定我检查了gtoclkout0（0））的模拟中效果很好。
没有我的设计没有逗号对齐。
我正在使用基于逻辑的DRU和框架......当我使用每个GTP的gtpclkout（1）时，一切都没问题，但我不能与其他GTP共享一个GTP的gtpclkout（1），即使所有线路速率和clks都是
一样。
问候，
马兹



以下为原文

Srinadh,
Thanks.

gtpclkout0(0) is for Tx and gtpclkout0(1) is for Rx.

From UG386,
 

It is said that REFCLKPLL can be ouput to FPGA logic via gtpclkout0(0), But you are right. If we "only" consider the frequency this clock is the same as rxrecclk in my design.
 

Do you find the design working in simulation? if you are using comma alignment, check the status signals of this module to start with.

Yes the tile0_gtp1 works well in simulation with gtpclkout0(1) and rxrecclk0 (I am not sure I checked the gtoclkout0(0)).


And no my desing doesn't have comma alignment. I am using a logic based DRU and framing and .... Everything is okay when I use each GTP's gtpclkout(1), but I cannot share one GTP's gtpclkout(1) with other GTPs, even though all the line rates and clks are the same.
 
Regards,
Maz

我应该说得更清楚。
gtpclkout0（0）用于TXOUTCLK，gtpclkout0（1）用于RXRECCLK。
您可以在共享的相同图片中找到它。
GTPCLKOUT（1）有路径。如果您正在共享GTPCLOUT（1），我也无法正确理解。
如果是，则应启用RXBUFFER。
这样，可以补偿gtp1和gtp0的RXRECCLK之间的小频率差异。
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以下为原文

I should have made it more clear. gtpclkout0(0) is for TXOUTCLK and
gtpclkout0(1) is for RXRECCLK. You can find this in the same picture you shared. There is path for GTPCLKOUT(1).

I do not understand correctly if you are sharing GTPCLOUT(1) also. If YES, you should be having the RXBUFFER enabled. This way small frequency differences between RXRECCLK of gtp1 and gtp0 can be compensated.

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Srinadh，
是的，我使用DCM将tile0_gtpclkout0（1）除以2，然后使用它来驱动tile0_usrclk20和tile0_usrclk21。
它适用于第一个但不适用于第二个。
是的，我正在使用RX缓冲区。
磁贴没有TX，没有对齐，没有OOB。
实际上我没有在PCS部件中使用任何东西，数据恢复和框架在Logic中完成。
GTP1使用GTP0_pll作为refclk，GTP的输入数据相同。
也许我应该禁用RX缓冲区并尝试使用时钟校正？
问候



以下为原文

Srinadh,
 
Yes, I am using a DCM to divide tile0_gtpclkout0(1) by 2, and then use it to drive tile0_usrclk20 and tile0_usrclk21. It works for the first one but not the second. And yes, I am using RX buffer .
 
The tile does not have TX, no alignment, no OOB. Actually I don't use anything in PCS part and data recovery and framing is done in Logic. GTP1 uses GTP0_pll as refclk and GTPs' input data are identical.
 
Maybe I should disable RX buffer and try to use clock correction?
 
Regards

如果您正在共享使用其他通道的RXRECCLK生成的RXUSRCLK，请查看RXBUFSTATUS。
它可能会报告上溢或下溢。如果禁用RX缓冲区，则无法使用时钟校正。
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以下为原文

If you are sharing the RXUSRCLKs generated using RXRECCLK of other lane, then please review RXBUFSTATUS. It could have overflow or underflow reported.

If you disable RX buffer, clock correction cannot be used.------------------------------------------------------------------------------
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------------------------------------------------------------------------------

那就对了。
GTP1 rx缓冲区溢出（状态为“010”），而GTP0状态为“000”....有趣。
这是为什么？
GTP之间的一切都是一样的。
输入流来自分发者，它们具有相同的内容和比特率。
一个缓冲区是如何溢出而另一个缓冲区完美的？
PS：如果我重置缓冲区并不重要，因为它会在短时间后再次溢出。
问候
马兹



以下为原文

 
That's right. GTP1 rx buffer overflows (status is "010") while GTP0 status is "000".... interesting. Why is that? everything is the same between the GTPs. Input streams are coming from a distributer and they have the same content and bit rate. How does one buffer overflow and the other work perfectly?
 
PS: It doesn't matter if I reset the buffer because it overflows again after a short time.
 
Regards
Maz

两个GTP的RXRECCLK可能不具有相同的准确度。
由于其中一个用作写时钟而另一个用作读时钟，因此可以观察到溢出/下溢。
您是否可以检查是否可以使用从TXOUTCLK生成的USRCLK用于RXUSRCLK？（或）您可以使GT Rx接口宽度与GT内部数据宽度相同，并使用结构FIFO来增加总线宽度。
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以下为原文

RXRECCLK from both GTPs may not have the same accuracy. Since one of them is used as a write clock and the other as a read clock, you could observe the overflow/underflow.

Can you check if you could use the USRCLKs generated from TXOUTCLK for RXUSRCLKs also?

(or)

You could make the GT Rx interface width to be same as the GT internal data width and use a fabric FIFO to increase the bus width.------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

上述第二种方法不需要额外的MMCM来生成RXUSRCLK，并且从TXOUTCLK生成的USRCLK可以用于结构FIFO的读时钟。
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以下为原文

The second approach above will not require additional MMCM for generating RXUSRCLKs and USRCLK generated from TXOUTCLK can be used for read clock of fabric FIFO.------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

对于第一种方法，我在实现之前模拟了设计，并观察到txoutclk0和gtpclkout0（0）与预期相同。
并且模拟工作正常（如果我让它运行一段时间，我不确定它是否会溢出）。
当我实现设计时，这次当我们使用gtpclkout0（1）时，两个缓冲区溢出而不是只有GTP1的缓冲区溢出。
只是为了澄清，txoutclk0和gtpoutclk0（1）有两个不同之处。
第一个区别是txoutclk0占空比为40/60但gtpoutclk0（1）为50/50。
第二个区别是txoutclk0与gtpclkout0（1）相比具有大约180度的相移。
考虑到第二种方法，我有一个用于DRU的NGC，它只接受20位数据。
这让我怀疑这种方法是否会对我们有所帮助。
我尝试注册10位输出，模拟很好，但我还没有成功实现它。
非常感谢venkata。
RegardsMaz



以下为原文

 
For the First approach, I simulated the design before implementation and I observed that txoutclk0 and gtpclkout0(0) are the same as expected. And simulation works fine (I am not sure whtether it overflows or not if I let it run for some time). When I implement the design, this time both buffers overflow instead of only GTP1's buffer overflowing when we were using gtpclkout0(1).
Just for clarification, txoutclk0 and gtpoutclk0(1) have two differences. the first difference is that txoutclk0 duty cycle is 40/60 but gtpoutclk0(1)'s is 50/50. And the second difference is that txoutclk0 has around 180 degrees phase shift comparing to gtpclkout0(1).
 
Considering the second approach, I have an NGC for DRU and it only accepts 20 bits of data. This makes me doubt if this method is gonna help us or not. I tried registering the 10 bit outputs and the simulation is fine but I have not yet succeeded in implementing it.
 
Thanks a lot venkata.
 
Regards
Maz

我只想添加两件事：
首先使用txoutclk进行仿真，在两个GTP RX缓冲区中不会发生溢出。
第二，因为我没有逗号对齐，我不能使用GTP的时钟校正。
问候
马兹



以下为原文

 
I just wanted to add two things:
 
First in simulation using txoutclk no overflow occurs in the two GTPs RX buffers.
And second because I have no comma alignment, I cannot use clock correction of GTP.
 
Regards
Maz