使用DCM在内部生成参考时钟频率有问题吗？

你好
参考时钟应由外部时钟源或东或西GT共享驱动。
您可以在UG386中找到详细信息。
不应使用使用DCM生成的内部时钟，因为它不能满足抖动要求并会导致错误。
http://www.xilinx.com/support/answers/43154.html
另请参阅以下链接
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan6-GTP-reference-clock-source/td-p/98008
问候，萨蒂什-----------------------------------------------
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以下为原文

Hi
 
 
The reference clock should be driven from the external clock sourse or from the east or west GT sharing.
 
You can find the details in UG386.
 
The internal clock generated using DCM should not be used as it will not meet the jitter requirements and will cause errors.
 
http://www.xilinx.com/support/answers/43154.html
 
Also refer the below link
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan6-GTP-reference-clock-source/td-p/98008
 
Regards,

Satish

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嗨萨蒂什，
感谢您的回复。
我知道外部时钟源是理想的选择。
然而，该板已经建成，无法更改。
有没有其他方法我可以让GTP使用内部时钟。
我目前的方案是从外部时钟振荡器获得27Mhz时钟。
我使用它生成148.5Mhz，然后将其提供给GTP参考时钟。
如果有任何方法可以使其与GTP一起使用，请告诉我。
问候
Ayusman



以下为原文

Hi Satish,
 
Thanks for your reply. I understand that an external clock source is the ideal choice. However the board is already built and cannot be changed. Is there any way else I can get the GTP to work with an internal clock.
 
My current scheme is that I get a 27Mhz clock from an external clock oscillator. I use that to generate 148.5Mhz and then give it to GTP reference clock. Please let me know if there is any way to get this to make it work with GTP.
 
Regards
Ayusman

你好
如果您没有任何选项来提供外部参考时钟。
您可以尝试使用GCLK端口，但请注意，这些时钟选项仅用于内部测试目的，不建议或不能保证正确操作。
如果抖动不符合上一篇文章中提到的要求值，则会出现性能问题，因为这些参考时钟端口具有最低的可用时钟性能，因为FPGA时钟资源可能会引入抖动，以便在高数据速率下工作。
有关使用GCLK选项的更多详细信息，请参阅UG386。
问候，萨蒂什-----------------------------------------------
--- --------------------------------------------请注意
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
---------------------------- ---------------------
----------------------



以下为原文

Hi
 
If you don't have any options to provide the external reference clock.
 
You can try using the GCLK ports, but kindly note that these clocking option is only for internal testing purposes and it is not recommended or can not guarantee the correct operation.
 
If the jitter is not in the required values as mentioned in the previous post,there will be performace issues as these reference clock ports have the lowest performance of the available clocking methods because FPGA clocking resources can introduce jitter for operation at high data rates.
 
Refer UG386 for more details on using GCLK option.
 
 
Regards,

Satish

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你好
谢谢。
我会用GCLK试一试，让你知道。
问候
Ayusman



以下为原文

Hi
 
Thanks. I will try it out with the GCLK and let you know.
 
Regards
Ayusman