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Gents,我有一个DCM_CLKGEN,可以在DIGILENT ATLYS(Spartan-6 FPGA)中为HD(1280x720p)生成74.25 MHz TMDS时钟。
该DCM_CLKGEN由DCM_SP驱动以获得74.25 MHz,并且PLL_BASE用于获得必需的clk_x10和clk_x2。 但是当我编译时,我获得以下警告消息: 时序:3159 - DCM,Clocking / TMDS_MASTER_DCM,属性DFS_OSCILLATOR_MODE未设置为PHASE_FREQ_LOCK。 输入时钟与此DCM的CLKFX或CLKFX180输出之间不存在相位关系。 必须使用FROM / TO约束来约束这些时钟域之间的数据路径。 (3次,一次im地图,其他在par和trce中) DCM位于名为Clocking的顶级模块中,原语是: TMDS_MASTER_DCM:DCM_CLKGEN 通用地图( CLKFXDV_DIVIDE => 2, - CLKFXDV分频值(2,4,8,16,32) CLKFX_DIVIDE => 100, - 除值 - D - (1-256) CLKFX_MULtiPLY => 33, - 乘以值 - M - (2-256) SPREAD_SPECTRUM =>“无”, - 扩频模式“无” STARTUP_WAIT => FALSE, - 延迟配置完成,直到DCM_CLKGEN被锁定 CLKIN_PERIOD => 10.000, - 以ns为单位指定的输入时钟周期 CLKFX_MD_MAX => 0.000 - 定时分析的最大M / D比 ) 港口地图( - 输入时钟 CLKIN => mclk, - 输入时钟(100MHz主时钟) - 输出时钟 CLKFX => clkfx_master, - 生成时钟输出(33MHz) CLKFX180 =>打开, - 生成的时钟输出180º相移 CLKFXDV => open, - 分频时钟输出 - 用于动态相移的端口 PROGCLK =>'0', - 用于M / D重配置的时钟输入 PROGEN =>'0', - 高电平有效程序使能 PROGDATA =>'0', - 用于M / D重配置的串行数据输入 PROGDONE => open, - 成功重新编程(高电平有效) - 其他控制和状态信号 FREEZEDCM =>'0', LOCKED => lock_master, - 锁定输出 STATUS =>打开, - DCM_CLKGEN状态 RST => reset - 复位输入引脚 ); 用户Jonathan Spaul在Re:Reg DCM_CLKGEN原语中提供了类似于解决方案的内容,但在我的情况下,我没有找到正确的FROM / TO约束来抑制此警告。 请问,你能说出如何定义正确的约束吗? 我已经尝试过以下约束: PIN“Clocking / TMDS_MASTER_DCM.CLKIN”TNM_NET = DCM_MASTER_CLKIN; PIN“Clocking / TMDS_MASTER_DCM.CLKFX”TNM_NET = DCM_MASTER_CLKFX; TIMESPEC TS_DCM_MASTER_DFS =从“DCM_MASTER_CLKIN”到“DCM_MASTER_CLKFX”20 ns; 但是我在地图处理后获得了其他警告: 警告:ConstraintSystem - TNM:DCM_MASTER_CLKIN已分发到DCM但是 没有推出新的TNM约束。 TNM在以下用户中使用 团体或规格: [StereoVision.ucf(310)] 警告:ConstraintSystem - TNM:DCM_MASTER_CLKFX已分发到DCM但是 没有推出新的TNM约束。 TNM在以下用户中使用 团体或规格: [StereoVision.ucf(310)] 你能帮帮我吗? 以上来自于谷歌翻译 以下为原文 Gents, I've a DCM_CLKGEN to generate 74.25 MHz TMDS clock for HD (1280x720p) in a DIGILENT ATLYS (Spartan-6 FPGA). This DCM_CLKGEN is driven by a DCM_SP to obtain thos 74.25 MHz, and a PLL_BASE to obtain clk_x10 and clk_x2 necessary. But when I compile I obtain the following warning messages: Timing:3159 - The DCM, Clocking/TMDS_MASTER_DCM, has the attribute DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK. No phase relationship exists between the input clock and CLKFX or CLKFX180 outputs of this DCM. Data paths between these clock domains must be constrained using FROM/TO constraints.(3 times, one im map, other in par and in trce) DCM is located in a top module called Clocking and the primitive is: TMDS_MASTER_DCM: DCM_CLKGENgeneric map ( CLKFXDV_DIVIDE => 2, -- CLKFXDV divide value (2, 4, 8, 16, 32) CLKFX_DIVIDE => 100, -- Divide value - D - (1-256) CLKFX_MULTIPLY => 33, -- Multiply value - M - (2-256) SPREAD_SPECTRUM => "NONE", -- Spread Spectrum mode "NONE" STARTUP_WAIT => FALSE, -- Delay config DONE until DCM_CLKGEN LOCKED CLKIN_PERIOD => 10.000, -- Input clock period specified in ns CLKFX_MD_MAX => 0.000 -- Maximum M/D ratio for timing anlysis)port map ( -- Input clock CLKIN => mclk, -- Input clock (100MHz Master Clock) -- Output clocks CLKFX => clkfx_master, -- Generated clock output (33MHz) CLKFX180 => open, -- Generated clock output 180º phase shift CLKFXDV => open, -- Divided clock output -- Ports for dynamic phase shift PROGCLK => '0', -- Clock input for M/D reconfiguration PROGEN => '0', -- Active HIGH program enable PROGDATA => '0', -- Serial data input for M/D reconfiguration PROGDONE => open, -- Successful re-programming (active HIGH) -- Other control and status signals FREEZEDCM => '0', LOCKED => lock_master, -- Locked output STATUS => open, -- DCM_CLKGEN status RST => reset -- Reset input pin); User Jonathan Spaul provided something similar to a solution at Re: Reg DCM_CLKGEN primitive but I did not found right FROM/TO constraint to supress this warnings inmy case. Please, could you tell how to define the right constraint? I already tried the following constraint: PIN "Clocking/TMDS_MASTER_DCM.CLKIN" TNM_NET = DCM_MASTER_CLKIN;PIN "Clocking/TMDS_MASTER_DCM.CLKFX" TNM_NET = DCM_MASTER_CLKFX;TIMESPEC TS_DCM_MASTER_DFS = FROM "DCM_MASTER_CLKIN" TO "DCM_MASTER_CLKFX" 20 ns; But I obtain other warning after map process: WARNING:ConstraintSystem - TNM : DCM_MASTER_CLKIN was distributed to a DCM but new TNM constraints were not derived. This TNM is used in the following user groups or specifications: Please could you help me? |
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