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大家好,
我在GMII接口中为以太网千兆位的Rx部分设置约束时遇到问题。 首先,我需要找到信号的实际细节: 我附上了IEEE规范的细节。 设置时间为2.0ns,保持时间为0.5ns。 其次,我需要找到如何定义约束: 在第206页附带的tri_mode_eth_mac_ug138.pdf文件中,给出了详细信息。 他们说的是我需要延迟数据,以便我可以在约束之前应用OFFSET。 第三,我需要让它适应我的代码 这是我现在对Rx部分的代码。 时钟: //输入来自Rx_clk引脚的接收时钟 IBUFG Rx_IBUFG(.I(Rx_clk),. O(Rx_clk_IBUFG)); BUFG Rx_BUFG(.I(Rx_clk_IBUFG),. O(Rx_clk_O)); assign MAC_rx_clk = Rx_clk_O; 数据&安培;结肠; // reg boundery信号 总是@(posedge MAC_rx_clk或posedge重置) 如果(重置) 开始 Rx_er_dl1 总是@(posedge MAC_rx_clk或posedge重置) 如果(重置) MCrs_dv 在其余代码中使用MCrs_dv 总是@(posedge MAC_rx_clk或posedge重置) 如果(重置) MRxD 在其余代码中使用MRxD 分配MRxErr = Rx_er_dl3; 在其余代码中使用MRxErr 根据第206页附带的totri_mode_eth_mac_ug138.pdf文件,我需要使用IODELAY2延迟数据。 但是,我是否需要在此处执行此操作,因为我已将数据延迟3个Rx_clk周期? 根据同一文档,我需要将约束定义为: tiMEGRP“IN_GMII”OFFSET = IN 2 ns有效2 ns在“gmii_rx_clk”之前; 其中IN_GMII是输入引脚,而gmii_rx_clk是输入时钟。 在我的情况下,IN_GMII是什么? MRxErr,MCrs_dv和MRxD或输入焊盘本身,即Rxd,Rx_dv,Rx_er 在我的情况下,gmii_rx_clk是什么?Max_rx_clk或垫本身Rx_clk? ethernet.pdf的tri_mode_eth_mac_ug138_约束6988 KB 以上来自于谷歌翻译 以下为原文 Hi All, I have problems setting up my constraints for the Rx part of the ethernet gigabit in GMII interface. First I need to find the actual details of the signals: I have attached the details of the IEEE specification. Setup time is 2.0ns and hold time is 0.5ns. Second I need to find how to define the constraint: In the tri_mode_eth_mac_ug138.pdf file attached at page 206 the details are given. What they say is that I need to delay the data so that I can then apply an OFFSET IN BEFORE constraint. Third, I need to adapt it to my code Here is my code for the Rx part right now. clock: //Input receive clock coming from Rx_clk pinIBUFG Rx_IBUFG ( .I(Rx_clk), .O(Rx_clk_IBUFG) );BUFG Rx_BUFG ( .I(Rx_clk_IBUFG), .O(Rx_clk_O) );assign MAC_rx_clk =Rx_clk_O;Data: //reg boundery signalsalways @ (posedge MAC_rx_clk or posedge Reset) if (Reset) begin Rx_er_dl1 <=0; Rx_er_dl2 <=0; //added delay on the Rx_er to match delay of Rx_dv Rx_er_dl3 <=0; Rx_dv_dl1 <=0; Rx_dv_dl2 <=0 ; Rxd_dl1 <=0; Rxd_dl2 <=0; end else begin Rx_er_dl1 <=Rx_er ; //received error Rx_er_dl2 <=Rx_er_dl1 ; Rx_er_dl3 <=Rx_er_dl2 ; Rx_dv_dl1 <=Rx_dv ; //received dataValid Rx_dv_dl2 <=Rx_dv_dl1 ; Rxd_dl1 <=Rxd ; //Rxd is receive dtata pins Rxd_dl2 <=Rxd_dl1 ; end always @ (posedge MAC_rx_clk or posedge Reset) if (Reset) MCrs_dv <=0; else if(Rx_dv_dl2) /// Received DataValid is high to indicate that valide data is present on the corresponding RxD MCrs_dv <=1; else MCrs_dv <=0;MCrs_dv is used throughout the rest of the code always @ (posedge MAC_rx_clk or posedge Reset) if (Reset) MRxD <=0; else if(Rx_dv_dl2) //If Received DataValid is high to indicate that valide data is present on the corresponding RxD MRxD <=Rxd_dl2; MRxD is used throughout the rest of the code assign MRxErr =Rx_er_dl3 ; MRxErr is used throughout the rest of the code According to tri_mode_eth_mac_ug138.pdf file attached at page 206, I need to delay the data using IODELAY2. HOWEVER, do I need to do this here since I already delay the data 3 Rx_clk cycles? According to the same document I need to define the constrain as: TIMEGRP "IN_GMII" OFFSET = IN 2 ns VALID 2 ns BEFORE "gmii_rx_clk"; where IN_GMII is the input pins and gmii_rx_clk the input clock. In my case IN_GMII is what? MRxErr, MCrs_dv and MRxD or the input pad themselves i.e. Rxd, Rx_dv, Rx_er In my case gmii_rx_clk is what? Max_rx_clk or the pad itself Rx_clk? |
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我试过这个
INST“Rxd [0]”TNM = IN_GMII; INST“Rxd [1]”TNM = IN_GMII; INST“Rxd [2]”TNM = IN_GMII; INST“Rxd [3]”TNM = IN_GMII; INST“Rxd [4]”TNM = IN_GMII; INST“Rxd [5]”TNM = IN_GMII; INST“Rxd [6]”TNM = IN_GMII; INST“Rxd [7]”TNM = IN_GMII; INST“Rx_er”TNM = IN_GMII; INST“Rx_dv”TNM = IN_GMII; TIMEGRP“IN_GMII”OFFSET = IN 2 ns有效2 ns,在“Rx_clk”之前; 并将此添加到Rxd IODELAY2#( .DATA_RATE(“SDR”),//,DDR .IDELAY_VALUE(0),// {0 ... 255} .IDELAY_TYPE(“FIXED”),//“DEFAULT”,“DIFF_PHASE_DETECTOR”,“FIXED”,“VARIABLE_FROM_HALF_MAX”,“VARIABLE_FROM_ZERO” .COUNTER_WRAPAROUND(“WRAPAROUND”),//,WRAPAROUND .DELAY_SRC(“IDATAIN”),//“IO”,“IDATAIN”,“ODATAIN” .SERDES_MODE(“MASTER”),//,MASTER,SLAVE .SIM_TAPDELAY_VALUE(49))// iodelay_Rxd( .IDATAIN(Rxd ),//来自主IOB的数据 .TOUT(),//三态信号到IOB .DOUT(),//将数据输出到IOB .T(1'b1),//来自OLOGIC / OSERDES2的三态控制 .ODATAIN(1'b0),//来自OLOGIC / OSERDES2的数据 .DATAOUT(),//输出数据1到ILOGIC / ISERDES2 .DATAOUT2(Rxd_delay ),//输出数据2到ILOGIC / ISERDES2 .IOCLK0(),//用于SDR / DDR校准的高速时钟 .IOCLK1(1'b0),//用于DDR校准的高速时钟 .CLK(),//控制信号的Fabric时钟 .CAL(),//校准控制信号 .INC(),//递增计数器 .CE(),//时钟启用 .RST(),//复位延迟线 。忙 ()) ; ,但即使IDELAY_VALUE为0,我也会得到3.5ns延迟,并且我有一个设置条件错误。 没有IODELAY2,我得到一个保持条件错误!! 我不明白一切,这就是为什么这给我带来了太多麻烦......但我会。 任何帮助都会被贬低 以上来自于谷歌翻译 以下为原文 I have tried the this INST "Rxd[0]" TNM = IN_GMII;INST "Rxd[1]" TNM = IN_GMII;INST "Rxd[2]" TNM = IN_GMII;INST "Rxd[3]" TNM = IN_GMII;INST "Rxd[4]" TNM = IN_GMII;INST "Rxd[5]" TNM = IN_GMII;INST "Rxd[6]" TNM = IN_GMII;INST "Rxd[7]" TNM = IN_GMII;INST "Rx_er" TNM = IN_GMII;INST "Rx_dv" TNM = IN_GMII; TIMEGRP "IN_GMII" OFFSET = IN 2 ns VALID 2 ns BEFORE "Rx_clk"; and added this to the Rxd IODELAY2 #( .DATA_RATE ("SDR"), // , but even with a IDELAY_VALUE of 0 I get 3.5ns delay and I have a setup condition error. Without the IODELAY2, I get a hold condition error!! I do not understand everything and this is why this gets me so much trouble... but I will. Any help would be apreciated |
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我现在正在使用DCM,因为延迟更容易预测。
我使用以下约束 TIMEGRP“IN_GMII”OFFSET = IN 2 ns有效2 ns在“Rx_clk”之前; 在DCM中相移-30度,它给了我以下内容: 所以我到处都有一个保持条件和一个大的保持松弛。 以上来自于谷歌翻译 以下为原文 I am using a DCM now as the delay is more predictable. I use the following constraint TIMEGRP "IN_GMII" OFFSET = IN 2 ns VALID 2 ns BEFORE "Rx_clk"; with a -30 degrees phase shift in the DCM it gave me the following : So I have a hold condition everywhere and a large hold slack. |
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