如何解决SPARTAN 3A项目的麻烦

tify;text-indent: 40px;">你好，
我对Xilinx 14.5 ISE工具存在重大（几个）问题。
我通过XILINX联盟计划获得完全许可。
我使用14.5 ISE Project Navigator开发设计，并使用XC3S400a-4ft256启动项目。
我使用了几个IP核，例如块公羊，Fifo's，Multiplier。
该项目是在C： Project  Project_A中创建的
当我在项目中的里程碑时，我将Project_A文件夹复制到存档文件夹并将其重命名为PROJECT_A_DATE。
问题1：
如果我然后决定我想在directiory C： Archive  Project  Project_A_DATE中打开存档项目并编译逻辑。
该项目有时会正确编译，有时它不会。
问题2：
我在设计之后发现我需要更大的FPGA 700a。
我去将项目设置更改为700a。
现在，当我打开项目时，我收到警告：
警告：ProjectMgmt  - 核心“mem_18x1024”的设备设置与ISE项目设置不匹配。设备不匹配“xc3s400a”与“xc3s700a”警告：ProjectMgmt  - 核心“fifo_36x512”的设备设置与ISE项目设置不匹配。
设备不匹配“xc3s400a”与“xc3s700a”警告：ProjectMgmt  - 核心'softr_cabon_40Hz'的设备设置与ISE项目设置不匹配。设备不匹配“xc3s400a”与“xc3s700a”警告：ProjectMgmt  - 核心设备设置'
softr_cabon_60Hz'与ISE项目设置不匹配。设备不匹配“xc3s400a”与“xc3s700a”警告：ProjectMgmt  - 核心'softr_cabon_83Hz'的设备设置与ISE项目设置不匹配。设备不匹配“xc3s400a”与“xc3s700a”
警告：ProjectMgmt  - 核心'softr_cabon_100Hz'的设备设置与ISE项目设置不匹配。设备不匹配“xc3s400a”与“xc3s700a”
等等...
问题3：
然后，我将Archive项目复制回与C：/ Project / Project_A相同的Path文件，并尝试重新编译。
有时它正确编译并且有时它没有工作。
经过几个小时试图弄清楚我们是否改变了源代码中的某些东西（我们没有改变），我重新启动了我的计算机（Windows 7）并重新打开了项目文件并重新启动并且它第一次运行。
我不敢再试一次。
现在我们（硬件工程师（设计硬件板））是惊慌失措的，因为他必须在周二进行EMC测试并转到首席工程师，现在造成了一个巨大的问题。
我们正在彻底解决我们所有的时序限制，并设置了XILINX FAE来完成我们的设计，以便我们消除它是一个时序问题。
我深知自己的时机不是问题，但我无法证明这一点。
我们的运行频率为25 MHz，是FPGA能够做到的10％......
正在运行的输出基本上如下所示：
输出1：输出std_logic（约束到引脚E16）
输出2：输出std_logic（约束到引脚T5）
在架构中：

输出1 以下为原文

Hello,

I am having major (SEVERAL) problems with Xilinx 14.5 ISE tools.  I have the Full license via XILINX alliance program.

I make developing a design using 14.5 ISE Project Navigator and started the project using XC3S400a-4ft256.

I used several IP cores such as block rams, Fifo's, Multiplier.  

The project was created in C:ProjectProject_A

When I am at a milestone in my project I copy the Project_A folder to a archive folder and rename it PROJECT_A_DATE.

Problem 1:

If I then decide I want to open up the archive project in directiory C:ArchiveProjectProject_A_DATE  and compile the logic.  The project sometimes compiles properly, sometimes it doesnt.

Problem 2:
I found out after designing that I am going to need a larger FPGA 700a for example.  I go and change the project settings to 700a.  

Now when I open up the Project I get the warnings:

WARNING:ProjectMgmt - The device settings for core 'mem_18x1024' do not match the ISE project settings.
Device mismatch "xc3s400a" vs. "xc3s700a"
WARNING:ProjectMgmt - The device settings for core 'fifo_36x512' do not match the ISE project settings.
Device mismatch "xc3s400a" vs. "xc3s700a"
WARNING:ProjectMgmt - The device settings for core 'softr_cabon_40Hz' do not match the ISE project settings.
Device mismatch "xc3s400a" vs. "xc3s700a"
WARNING:ProjectMgmt - The device settings for core 'softr_cabon_60Hz' do not match the ISE project settings.
Device mismatch "xc3s400a" vs. "xc3s700a"
WARNING:ProjectMgmt - The device settings for core 'softr_cabon_83Hz' do not match the ISE project settings.
Device mismatch "xc3s400a" vs. "xc3s700a"
WARNING:ProjectMgmt - The device settings for core 'softr_cabon_100Hz' do not match the ISE project settings.
Device mismatch "xc3s400a" vs. "xc3s700a"

etc...

Problem 3:

I then Copied the Archive project back into the same Path files as C:/Project/Project_A and tried recompiling. AGAIN sometime it compiled correctly and worked sometimes it didn't.  

After hours of trying to figure out if we changed somethign in the source code (which we didn't) I restarted my computer(Windows 7) and reopened the project files and recomipled and it worked the first time.  I did not dare to try again.

Now our (Hardware Engineer(designed the Hardware of the board)) is paniccing cause he has to do an EMC test on Tuesday and goes to the Lead engineer and now created a huge problem.

We are sweeping through all our Timing constraints and have set up with a XILINX FAE to go over our design so that we eliminate that it was a Timing issue.

I know deep in my gut that timing is not an issue, but I can't prove it.   We are running at 25 MHz which is 10% of what the FPGA is capable of doing...  
The Output that was functioning basically looked like this:

Output 1 : out std_logic    (constrained to pin E16)
Output 2: out std_logic   ( constrained to pin T5)

In the architecture:

Output 1 <= signal 1;
Output 2 <= signal 1;


I feel like the Xilinx Software got bugged and IP cores/ Tools got confused with the Paths and somehow compiled my project incorrectly.

Has anything like this happened before?

I need to try and explain how this happened and how to fix it, before we start chasing things that are irrelevant and waste even more of my time.  I already wasted 8 hours chasing a ghost.  


Thanks

C