[问答]

请问在2个MPMC实例之间共享bufpll_mcb对吗？

问答对人有帮助，内容完整，我也想知道答案 0 我正在使用EDK（版本13.2）来实现具有3个MPMC实例的DDR3接口。我希望其中2个实例使用常见的BUFPLL_MCB。 UG388，图3-3显示了我想要做的事情。在表2中的“LogiCORE IP多端口存储器控制器”（DS643）中，有一个参数“C_MSB_USE_EXTERNAL_BUFPLL”，用于控制MPMC是否实例化BUFPLL_MCB。我已经在EDK中使用GUI来配置每个MPMC和clock_generator实例，但是没有看到如何设置此参数。我尝试在EDK生成的文本网表中设置参数，但MAP报告仍然显示 BUFPLL_MCB的数量：4个中的3个75％这导致失败，因为其他BUFPLL已经用于其他purporses。在EDK中，我在连接到MCB3和MCB4的MPMC实例之间共享时钟信号。我错过了设置此参数的位置吗？我仔细查看了文档并相信我在相应的MCB之间共享时钟。也许我在分享错误的实例？谢谢你的帮助。安德烈斯塔梅兹以上来自于谷歌翻译以下为原文 I am using the EDK (Version 13.2) to implement a DDR3 interface with 3 MPMC instances. I would like 2 of these instances to use a common BUFPLL_MCB. UG388, figure 3-3 shows what I am trying to do. In the "LogiCORE IP Multi-Port Memory Controller" (DS643) on Table 2 there is a parameter "C_MSB_USE_EXTERNAL_BUFPLL" that controls whether or not the MPMC instantiates a BUFPLL_MCB. I've used the GUI in the EDK for configuring each MPMC and clock_generator instance but do not see how to set this parameter. I tried setting the parameter in the textual netlist generated from the EDK, but the MAP report still shows Number of BUFPLL_MCBs: 3 out of 4 75% This causes failure since the other BUFPLLs are already used for other purporses. In the EDK I have shared the clock signals between the MPMC instances connected to MCB3 and MCB4. Am I missing where to set this parameter? I've looked through documentation thoroughly and believe I'm sharing clocks between the appropriate MCBs. Maybe I'm sharing the wrong instances? Thanks for your help. Andres Tamez 0
2019-6-20 16:34:03　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答举报李韵相关推荐 • 将GCLK输入连接到多个PLL 2161 • 请问Spartan6对同一银行的BUFPLL和MCB的限制是什么？ 2930 • 时钟区域分配失败 645 • 一个MCB模块的地址和控制是否可以共享到2个DDR3 1769 • 如何利用SP605 TI_ads5282使用xapp1064进行反序列化数据配置？ 2360 • Ise 14.1无法在我需要的频率中合成MCB 3960 • 如何将PLL / BUFPLL保留在我的项目中 2291 • BUFIO2的输入信号无法路由 3620 • 有办法刷新MCB读FIFO而不必将其计时直到空吗？ 645 • 在virtex 4 Ml403中采用Microblaze和PPC进行双处理器设计的问题如何解决 1985 2个回答

答案对人有帮助，有参考价值 0 像往常一样，当我组织思考并寻求帮助时，我偶然发现了一个解决方案。首先，我在EDK创建的MHS文件中手动添加了“C_MCB_USE_EXTERNAL_PLL”。然后我发现从MPMC v6.04a指南中阅读以下内容后，我的时钟共享连接不正确。设计已成功通过Mapping，并在P＆amp; R。（http://www.xilinx.com/support/documentation/ip_documentation/mpmc/v6_04_a/mpmc.pdf）：当两个MPMC位于设备的同一侧时，它们必须都在相同的存储器时钟上运行。以下是微处理器硬件规范（MHS）文件示例，说明当两个MPMC位于其上时两个MPMC如何使用级联时钟连接。该装置的同一侧：BEGIN mpmcPARAMETER INSTANCE = MPMC_0 ... PORT MPMC_Clk_Mem_2x_bufpll_o = MPMC_Clk_Mem_2x_bufpll_oPORT MPMC_Clk_Mem_2x_180_bufpll_o = MPMC_Clk_Mem_2x_180_bufpll_oPORT MPMC_Clk_Mem_2x_CE0_bufpll_o = MPMC_Clk_Mem_2x_CE0_bufpll_oPORT MPMC_Clk_Mem_2x_CE90_bufpll_o = MPMC_Clk_Mem_2x_CE90_bufpll_oPORT MPMC_PLL_Lock_bufpll_o = MPMC_PLL_Lock_bufpll_oENDBEGIN mpmcPARAMETER INSTANCE = MPMC_1PARAMETER C_MCB_USE_EXTERNAL_BUFPLL = 1 ... PORT MPMC_Clk_Mem_2x = MPMC_Clk_Mem_2x_bufpll_oPORT MPMC_Clk_Mem_2x_180 = MPMC_Clk_Mem_2x_180_bufpll_oPORT MPMC_Clk_Mem_2x_CE0 = MPMC_Clk_Mem_2x_CE0_bufpll_oPORT MPMC_Clk_Mem_2x_CE90 = MPMC_Clk_Mem_2x_CE90_bufpll_oPORT MPMC_PLL_Lock = MPMC_PLL_Lock_bufpll_oEND 在原帖中查看解决方案以上来自于谷歌翻译以下为原文 As usual as soon as I organize thoughts and ask for help I stumble across a solution. First, I added the "C_MCB_USE_EXTERNAL_PLL" manually in the MHS file created by the EDK. Then I discovered that my clock sharing was wired incorrectly after reading the following from the MPMC v6.04a guide. Design has successfully passed Mapping and is in P&R. (http://www.xilinx.com/support/documentation/ip_documentation/mpmc/v6_04_a/mpmc.pdf): When two MPMCs are located on the same side of the device, they must both operate on the same memory clock. The following is an Microprocessor Hardware Specification (MHS) file example of how the two MPMCs use cascaded clock connections when they are both located on the same side of the device: BEGIN mpmc PARAMETER INSTANCE = MPMC_0 ... PORT MPMC_Clk_Mem_2x_bufpll_o = MPMC_Clk_Mem_2x_bufpll_o PORT MPMC_Clk_Mem_2x_180_bufpll_o = MPMC_Clk_Mem_2x_180_bufpll_o PORT MPMC_Clk_Mem_2x_CE0_bufpll_o = MPMC_Clk_Mem_2x_CE0_bufpll_o PORT MPMC_Clk_Mem_2x_CE90_bufpll_o = MPMC_Clk_Mem_2x_CE90_bufpll_o PORT MPMC_PLL_Lock_bufpll_o = MPMC_PLL_Lock_bufpll_o END BEGIN mpmc PARAMETER INSTANCE = MPMC_1 PARAMETER C_MCB_USE_EXTERNAL_BUFPLL = 1 ... PORT MPMC_Clk_Mem_2x = MPMC_Clk_Mem_2x_bufpll_o PORT MPMC_Clk_Mem_2x_180 = MPMC_Clk_Mem_2x_180_bufpll_o PORT MPMC_Clk_Mem_2x_CE0 = MPMC_Clk_Mem_2x_CE0_bufpll_o PORT MPMC_Clk_Mem_2x_CE90 = MPMC_Clk_Mem_2x_CE90_bufpll_o PORT MPMC_PLL_Lock = MPMC_PLL_Lock_bufpll_o END View solution in original post

2019-6-20 16:51:19 评论举报李妍

答案对人有帮助，有参考价值 0 像往常一样，当我组织思考并寻求帮助时，我偶然发现了一个解决方案。首先，我在EDK创建的MHS文件中手动添加了“C_MCB_USE_EXTERNAL_PLL”。然后我发现从MPMC v6.04a指南中阅读以下内容后，我的时钟共享连接不正确。设计已成功通过Mapping，并在P＆amp; R。（http://www.xilinx.com/support/documentation/ip_documentation/mpmc/v6_04_a/mpmc.pdf）：当两个MPMC位于设备的同一侧时，它们必须都在相同的存储器时钟上运行。以下是微处理器硬件规范（MHS）文件示例，说明当两个MPMC位于其上时两个MPMC如何使用级联时钟连接。该装置的同一侧：BEGIN mpmcPARAMETER INSTANCE = MPMC_0 ... PORT MPMC_Clk_Mem_2x_bufpll_o = MPMC_Clk_Mem_2x_bufpll_oPORT MPMC_Clk_Mem_2x_180_bufpll_o = MPMC_Clk_Mem_2x_180_bufpll_oPORT MPMC_Clk_Mem_2x_CE0_bufpll_o = MPMC_Clk_Mem_2x_CE0_bufpll_oPORT MPMC_Clk_Mem_2x_CE90_bufpll_o = MPMC_Clk_Mem_2x_CE90_bufpll_oPORT MPMC_PLL_Lock_bufpll_o = MPMC_PLL_Lock_bufpll_oENDBEGIN mpmcPARAMETER INSTANCE = MPMC_1PARAMETER C_MCB_USE_EXTERNAL_BUFPLL = 1 ... PORT MPMC_Clk_Mem_2x = MPMC_Clk_Mem_2x_bufpll_oPORT MPMC_Clk_Mem_2x_180 = MPMC_Clk_Mem_2x_180_bufpll_oPORT MPMC_Clk_Mem_2x_CE0 = MPMC_Clk_Mem_2x_CE0_bufpll_oPORT MPMC_Clk_Mem_2x_CE90 = MPMC_Clk_Mem_2x_CE90_bufpll_oPORT MPMC_PLL_Lock = MPMC_PLL_Lock_bufpll_oEND 以上来自于谷歌翻译以下为原文 As usual as soon as I organize thoughts and ask for help I stumble across a solution. First, I added the "C_MCB_USE_EXTERNAL_PLL" manually in the MHS file created by the EDK. Then I discovered that my clock sharing was wired incorrectly after reading the following from the MPMC v6.04a guide. Design has successfully passed Mapping and is in P&R. (http://www.xilinx.com/support/documentation/ip_documentation/mpmc/v6_04_a/mpmc.pdf): When two MPMCs are located on the same side of the device, they must both operate on the same memory clock. The following is an Microprocessor Hardware Specification (MHS) file example of how the two MPMCs use cascaded clock connections when they are both located on the same side of the device: BEGIN mpmc PARAMETER INSTANCE = MPMC_0 ... PORT MPMC_Clk_Mem_2x_bufpll_o = MPMC_Clk_Mem_2x_bufpll_o PORT MPMC_Clk_Mem_2x_180_bufpll_o = MPMC_Clk_Mem_2x_180_bufpll_o PORT MPMC_Clk_Mem_2x_CE0_bufpll_o = MPMC_Clk_Mem_2x_CE0_bufpll_o PORT MPMC_Clk_Mem_2x_CE90_bufpll_o = MPMC_Clk_Mem_2x_CE90_bufpll_o PORT MPMC_PLL_Lock_bufpll_o = MPMC_PLL_Lock_bufpll_o END BEGIN mpmc PARAMETER INSTANCE = MPMC_1 PARAMETER C_MCB_USE_EXTERNAL_BUFPLL = 1 ... PORT MPMC_Clk_Mem_2x = MPMC_Clk_Mem_2x_bufpll_o PORT MPMC_Clk_Mem_2x_180 = MPMC_Clk_Mem_2x_180_bufpll_o PORT MPMC_Clk_Mem_2x_CE0 = MPMC_Clk_Mem_2x_CE0_bufpll_o PORT MPMC_Clk_Mem_2x_CE90 = MPMC_Clk_Mem_2x_CE90_bufpll_o PORT MPMC_PLL_Lock = MPMC_PLL_Lock_bufpll_o END

2019-6-20 17:01:02 评论举报李妍