请问Spartan6对同一银行的BUFPLL和MCB的限制是什么？

对此设计进行故障排除有很多可能性在您将此问题排除在逻辑结论之前，您没有引脚排列，电路板布局或产品设计。
建议：
1.当您在寻找解决方案的墙上敲打头时，打开一个Web箱以获得Xilinx的直接支持。
2.在调试方面，不要停止。
来自UG382的这篇文章可能提供一个线索：
BUFPLL_MCB在同一个库中包含两个BUFPLL。
因此，BUFPLL_MCB和BUFPLL不能同时使用。
您是否可以灵活地将差分串行输入移至偶数（非MCB）IO组之一？
（不要忘记更新.UCF约束，包括IOSTANDARD）。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
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在原帖中查看解决方案



以下为原文

There are a large number of possibilities for troubleshooting this design  Until you troubleshoot this problem to its logical conclusion, you don't have a pinout, a circuit board layout, or a product design.
 
Suggestions:
 
1.  While you are beating your heads against a wall searching for the solution, open a webcase for direct Xilinx support.
2.  On the debugging side, don't stop.
 
This text from UG382 may provide a clue:
The BUFPLL_MCB contains two BUFPLLs within the same bank. As a result, the BUFPLL_MCB and BUFPLL cannot be used at the same time.
 
Do you have the flexibility to move the differential serial inputs to one of the even-numbered (non-MCB) IO banks? (don't forget to update the .UCF constraints, including IOSTANDARD).
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.View solution in original post

“LVDS”输入由于与DDR2内存控制器共享相同的IO库，因此可能仅限于1.8V差分IO标准之一。
见DS162，表8。
我可能错了，因为你只使用输入。
值得一试。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

The "LVDS" inputs, because they share the same IO bank as the DDR2 memory controller, may be limited to one of the 1.8V differential IO standards.  See DS162, Table 8.
 
I may be wrong on this, as you are using input only.  It's worth checking.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

莫因，
听起来很有希望;
我刚刚将.ucf文件中的IOSTANDARD从LVDS_33更改为DIFF_SSTL18_II，这与用于DDR2差分信号的相同。
但错误保持不变。
还有DIFF_SSTL_18_I，DIFF_HSTL_II，LVDS_25  - 所以我假设，它不是IO标准的问题，但是某种程度上与我用于810MHz的PLL和MCB PLL或它们的缓冲器之间的难以实现有关。
但这只是基于我缺乏知识的一些猜测。
干杯，
WK



以下为原文

Moin,

Sounds promising; i just changed the IOSTANDARD in the .ucf file from LVDS_33 to DIFF_SSTL18_II, which is the same, as is used for the DDR2 differential signals. But the error keeps being the same. Also with DIFF_SSTL_18_I, DIFF_HSTL_II, LVDS_25 - so i assume, it's not a problem of the IO standard but somehow related to difficulites between the PLL i use for the 810MHz and the MCB PLL or their buffers. But this is just some guessing based on my lack of knowledge.

Cheers,

WK

WK和Moin，
有可能存在多个问题。
建议你删除4个输入差分对的.UCF引脚分配，让ISE自动分配封装引脚。
同时保持WK对IOSTANDARD的更改。
然后看看地点和路线会发生什么。
Bonne机会！
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

WK and Moin,
 
It is possible that there are multiple problems.
 
Suggest you remove the .UCF pin assignments for the 4 input diff pairs, and let ISE auto-assign the package pins.  Also keep the IOSTANDARD change made by WK.  Then see what happens with place and route.
 
Bonne chances!
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

莫因，
嗯，现在它已经开始了......
这是我做的：
*根本没有ucf文件会导致某些内存引脚出错。
*所以我添加了从MIG获得的.ucf，其中有一些关于时钟信号的微小变化（来自PLL，而不是来自引脚，因为它是MIG用户设计中的情况）。
我没有添加任何关于我的4个ISERDES输入 - 结果：与我的第一篇文章中的错误相同。
*我在ucf中添加了8个引脚定义，如：
NET bla_in_p IOSTANDARD = DIFF_SSTL18_II;＃|
LOC = BANK1;
NET bla_in_n .... yadayada ...
...
有和没有LOC = BANK1指令 - 没有变化：每次出现与我首先发布的相同的错误消息。
:-(
干杯，
WK



以下为原文

Moin,
 
Hm, now it's getting weired..
Here's what i did:
* No ucf file at all results in errors on some memory pins.
* So i added the .ucf i got from the MIG, with some minor changes concerning the clock signal (which comes from the PLL instead from pins as it is the case in the MIG user design). I added nothing at all about my 4 ISERDES inputs - result: The same error as in my first post.
* I added 8 pin definitions in the ucf, like:
 
NET bla_in_p<0> IOSTANDARD = DIFF_SSTL18_II;# | LOC=BANK1;
NET bla_in_n<0> ....yadayada...
...
with and without the LOC=BANK1 directive  - no changes: everytime the same error message as i posted first. :-(
 
Cheers,
WK
 

没有ISERDES部分的设计似乎也可以编译而没有错误，这会导致建筑过程中断。
这仍然是真的吗？
如果是这样，也许您应该发布您的顶级代码。
可以在ISERDES时钟连接的细节中发现这个谜团。
135MHz GCLK0输入是用于MCB的PLL还是用于ISERDES的PLL？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

The Design without the ISERDES part also seems to be compilable without errors, which cause interruption of the building process.
 
Is this still true?  If so, perhaps you should post your top-level code.  The mystery may be discovered in the details of the ISERDES clock connections.  Is the 135MHz GCLK0 input used for both the PLL for the MCB and the PLL for the ISERDES?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

莫因，
我通过BUFG使用PLL的输出2（270MHz）作为MCB的输入。
eteam00写道：
没有ISERDES部分的设计似乎也可以编译而没有错误，这会导致建筑过程中断。
这仍然是真的吗？
我想是这样。
我这么想的是，当我不使用ISERDES2的输出时它会编译 - 然后它们（以及整个810MHz PLL / BUFPLL废话）将被优化掉，并且由于运行编译器而得到一个比特流文件
。
构建过程的成功或失败可以减少到这部分代码：
crappy_asits：process（asits0，asits1，asits2，asits3）begin-- aux3 aux3 end process;
如果编译如上所示，它的工作原理。
如果我将注释放在下面一行，它就会失败（因为那时使用的是asits0..3信号而且不能“优化掉”。
（两种情况下ucf文件保持不变）。
aux3在某些FPGA引脚处结束，asits0..3是来自我的4个iserdes2组件的信号。
干杯
WK



以下为原文

Moin,
 
I use the output2 of the PLL (270MHz)  via BUFGs as input to the MCB.

eteam00 wrote:
The Design without the ISERDES part also seems to be compilable without errors, which cause interruption of the building process.
 
Is this still true? 

I think so. What me makes thinking so is, that it compiles, when i don't use the outputs of the ISERDES2 - then they (and the whole 810MHz PLL/BUFPLL crap) will be optimized away and i get a bitstreamfile as result of running the compiler.
 
Success or fail of the building process can be reduced to this part of code:
crappy_asits : process(asits0,asits1,asits2,asits3)
begin
--  aux3 <= "00" & (asits0 xor asits1 xor asits2 xor asits3);
    aux3 <= "000000000000";
end process; if compiled as shown above, it works. If i put the comments one line below, it fails (because then the asits0..3 signals are used and cannot be "optimized away".
(ucf file stays the same in both cases).
 
aux3 ends at some FPGA pins, asits0..3 are signals coming from my 4 iserdes2-components.
 
Cheers
WK
 
 
 

对此设计进行故障排除有很多可能性在您将此问题排除在逻辑结论之前，您没有引脚排列，电路板布局或产品设计。
建议：
1.当您在寻找解决方案的墙上敲打头时，打开一个Web箱以获得Xilinx的直接支持。
2.在调试方面，不要停止。
来自UG382的这篇文章可能提供一个线索：
BUFPLL_MCB在同一个库中包含两个BUFPLL。
因此，BUFPLL_MCB和BUFPLL不能同时使用。
您是否可以灵活地将差分串行输入移至偶数（非MCB）IO组之一？
（不要忘记更新.UCF约束，包括IOSTANDARD）。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

There are a large number of possibilities for troubleshooting this design  Until you troubleshoot this problem to its logical conclusion, you don't have a pinout, a circuit board layout, or a product design.
 
Suggestions:
 
1.  While you are beating your heads against a wall searching for the solution, open a webcase for direct Xilinx support.
2.  On the debugging side, don't stop.
 
This text from UG382 may provide a clue:
The BUFPLL_MCB contains two BUFPLLs within the same bank. As a result, the BUFPLL_MCB and BUFPLL cannot be used at the same time.
 
Do you have the flexibility to move the differential serial inputs to one of the even-numbered (non-MCB) IO banks? (don't forget to update the .UCF constraints, including IOSTANDARD).
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

莫因，
eteam00写道：
来自UG382的这篇文章可能提供一个线索：
BUFPLL_MCB在同一个库中包含两个BUFPLL。
因此，BUFPLL_MCB和BUFPLL不能同时使用。
- 鲍勃埃尔金德
好;
就是这样 - 非常感谢找到这句话。
这正是我怀疑的限制（见本帖的标题）。
为了让你和我更加困惑，昨天我意外地没有删除我传播到文件中的所有“属性LOC”。
所以昨天它也用不受约束的针脚不起作用。
现在它似乎编译，当我将我的ISERDES2单元格移动到bank0。
我的同事，做PCB现在会“很有趣”......
干杯
WK



以下为原文

Moin,

eteam00 wrote:

This text from UG382 may provide a clue:

The BUFPLL_MCB contains two BUFPLLs within the same bank. As a result, the BUFPLL_MCB and BUFPLL cannot be used at the same time.
 

 -- Bob Elkind

OK; thats it - thanks a lot for finding this sentence. This is exactly the limitation i suspected (see title of this thread). to confuse you and me more, yesterday  i accidently did not remove all of the "attribute LOC" things i had spread over my files. So yesterday it also with pins unconstrained didn't work. Now it seems to compile, when i move my ISERDES2 cells to bank0.
My colleague, doing the PCB will have "much fun" now...
 
Cheers
WK
 
 

亲爱的大家，
我确实有一个非常类似的问题。
我必须在连接DDR2模块的同一个bank上有几个LVDS输入。
因此，该银行的电压为1.8V。
但是，我确实有一个产生LVDS信号的外部设备。
该LVDS信号符合EIA / TIA-644标准（Vcm = 1.25V）
现在我的问题，
能否在1.8V供电的存储体上正确接收此LVDS信号？
我应该计划使用外部终端电阻吗？
非常感谢您的建议。
最好的祝福
Georg P. Israel



以下为原文

Dear All,
 
I do have a very similar issue.
I have to have a couple of LVDS inputs on the same bank where I have connected a DDR2 module.
Due to this, the bank is powered with 1.8V.
However, I do have an external device that generates LVDS signals.
This LVDS signals are EIA/TIA-644 standard conforming (Vcm = 1.25V)
 
Now my question,
will I be able to correctly receive this LVDS signals on the 1.8V powered bank?
Should I plan to use external termination resistors for this?
 
Your advice will be most appreciated.
 
Best regards
 
Georg P. Israel