请问我该如何正确定义/获得在Nexys2板上工作的5MHz时钟？

Toks，我假设您的意思是50 MHz（因为那是连接到该板上B8引脚的振荡器的频率）。您是否检查过时钟是否正常工作（使用示波器）？我会从一个非常简单的开始
设计，就像一个计数器，并使用计数器将时钟分频为一个闪烁某些LED的信号。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Toks,

I am assuming you meant 50 MHz (as that is the frequency of the oscillator connected to pin B8 on that board).

Have you checked to see that the clock is working (with an oscilloscope)?

I would start with a very simple design, like a counter, and using the counter to divide the clock down to a signal that blinks some LEDs.
Austin Lesea
Principal Engineer
Xilinx San Jose

你好先生，
是的先生，我指的是板载的50MHz时钟。
是的，这就是我真正想做的事情，至少是为了测试时钟是否正常工作。
我试过示波器，我没有看到任何合理的东西。
配置：5MHz，内部，在核心IP期间>> FPGA功能和设计>>斯巴达3E-3A >>单个DCM_SP等）在我的代码中实例化，通过pmod输出做Osc，但我什么也看不见。
几天前，我尝试了一个24位波纹计数器，我看到LED闪烁，但我不知道结果，因为即使我在UCF文件中没有使用的LED引脚也闪烁;
所以我编辑了我的UCF文件以使用PMOD但我的Osc上没有显示任何内容。
我的OSC是功能性的，因为我有一个功能，我可以从我的osc（来自Rigol的200MHz）的功能上看到我的波形。
先生，例如用一个计数器，通过做if（clk'event和clk ='1'）然后......这不应该使用板载时钟或者我真的需要
每当我需要时钟输入时，通过核心实例进行实例化？
问候
Toks



以下为原文

hello sir,
 
Yes sir, im referring to the 50MHz clock onboard.
 
Yes, that is what I really want to do, at least to test if the clock is working.
 
Ive tried with an oscilloscope, and I dont see anything reasonable.
 
Configuration: 5MHz, Internal, during the Core IP >> FPGA features and design >> spartan 3E-3A >> single DCM_SP etc)  instantiated in my code, out via the pmod do the Osc, but I dont see anything.
 
a couple of days ago, I tried a 24bit ripple counter, and I saw the LEDs blinking but I wasnt definite with the result, as even the LED pins that I didnt use in my UCF file were blinking as well; so I edited my UCF file to use the PMOD but nothing displayed on my Osc.
 
My OSC is functional, coz I have a func-gen and I can see my waveform from the func-gen on my osc(a 200MHz from Rigol).
 
Sir, for example with a counter, by doing if(clk'event and clk='1') then............. isnt this supposed to use the onboard clock or do I really have to instantiate it through the core-gen everytime I need a clock input?
 
regards
Toks
 
 

Toks，不，你不必使用core-gen。
您是否使用FPGA_editor检查了设计？
它是否连接到正确的引脚？如果示波器没有显示正确的信号，获得一个有效的示波器，或者学习如何使用你的示波器：必须快速检查一下是否正常工作！如果信号名称
在BUFG上是'时钟'然后IF事件被执行，并且= 1.该引脚可能有不同的名称，因为它在BUFG之前。
BUFG之前的名称与BUFG之后使用的名称不同...... BUFG应该在您的verilog或VHDL代码中，直接实例化。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Toks,

No, you don't have to use core-gen.  Have you examined the design with FPGA_editor?  Does it connect to the right pins?

If the oscilloscope does not display the proper signals, get a scope that works, or learn how to use the one you have:  it is a must to quickly check that things are working!

If the signal name on the BUFG is 'clock' then the IF statement gets executed on the event, and =1.

The pin may have a different name, as that is BEFORE the BUFG.  The name BEFORE the BUFG is different from the name used AFTER the BUFG.....

The BUFG should be in your verilog or VHDL code, instantiated directly.Austin Lesea
Principal Engineer
Xilinx San Jose

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/sim.pdfsee第30页
Austin Lesea主要工程师Xilinx San Jose



以下为原文

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/sim.pdf

see page 30Austin Lesea
Principal Engineer
Xilinx San Jose

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/7series_hdl.pdfbetter第168页
Austin Lesea主要工程师Xilinx San Jose



以下为原文

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/7series_hdl.pdf

better page 168

Austin Lesea
Principal Engineer
Xilinx San Jose